pFET Nanosheet Channel Capping for Threshold Voltage Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nanosheet FET devices face nonuniformity in threshold voltage (Vt) across channel regions, leading to reduced device performance, particularly in pFETs where the Vt difference between top and bottom surfaces can be as high as 100 mV, affecting overall device efficiency.
Innovation Solution
Incorporating a thin SiGe capping layer with lower Ge content on the uppermost active semiconductor layer of the nanosheet stack to address Vt nonuniformity, thereby improving Vt uniformity and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a nanosheet stack is used to reduce device footprint, then device density increases, but threshold voltage nonuniformity worsens
Solution Approach 1:
The patent applies local quality by forming a capping layer specifically on the uppermost channel region of the nanosheet stack. This localized modification targets the specific area where threshold voltage nonuniformity occurs (the top surface) without affecting other regions. The capping layer is selectively deposited only on exposed channel regions that are not covered by gate structures, thereby locally adjusting the electrical properties to compensate for the nonuniformity inherent in stacked nanosheet architectures.
2Area of stationary object
If multiple stacked nanosheets are implemented, then device footprint reduces, but threshold voltage control deteriorates
Solution Approach 1:
The capping layer is selectively applied only to specific regions of the nanosheet stack - namely the uppermost channel regions that are not covered by gate structures. This localized approach allows differential control of threshold voltage across different parts of the stacked structure, compensating for the inherent nonuniformity while maintaining the compact multi-layer architecture.
Solution Approach 2:
The patent changes physical parameters by introducing a capping layer with specific material composition and thickness on the uppermost channel regions. This modifies the local electrical characteristics, work function, and charge distribution at the channel surface, thereby adjusting the threshold voltage parameter locally to achieve uniformity across the stacked structure.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a pFET transistor formed on the semiconductor substrate. The pFET transistor includes a plurality of channel regions. An uppermost channel region of the plurality of channel regions includes an uppermost active semiconductor layer and a capping layer formed on the uppermost active semiconductor layer.