P-FET Dipole Layer Stack for Vt Shift Without EOT Penalty

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Solution Overview

Problem

The miniaturization of transistors in integrated circuits faces challenges in maintaining switching speeds without incurring failures, particularly in controlling device structure dimensions and achieving efficient p-type dipole materials with Vt shift without equivalent oxide thickness (EOT) penalty, as the technology migrates from planar to FinFET structures.

Innovation Solution

The implementation of a dipole region comprising an interlayer dielectric, a high-κ dielectric material, and a dipole layer, specifically using materials like titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), and tantalum oxide (TaO), deposited using atomic layer deposition, to enhance the work function and achieve significant Vt shift with minimal EOT increase.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistor dimensions are scaled down to increase functional density, then the number of components per chip increases, but device structure control becomes more difficult and switching speeds deteriorate

Engineering Contradiction:
Improvefunctional densityVSAvoiddevice structure control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The gate dielectric is segmented into multiple functional layers: a first dielectric layer (high-κ material) and a second dielectric layer (low-κ material). This segmentation allows each layer to perform specific functions - the high-κ layer provides strong electric field control while the low-κ layer provides electrical isolation - thereby maintaining manufacturing precision and switching performance even as overall device dimensions are scaled down to increase functional density.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If conventional dielectric materials are used in FinFET structures, then manufacturing is simpler, but multi-threshold voltage control becomes limited

Engineering Contradiction:
Improvemulti-Vt controlVSAvoidwork function layer requirements
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by using different dielectric materials with distinct properties in different regions/layers of the gate structure. The high-κ dielectric material is specifically positioned to provide strong field control for threshold voltage adjustment, while the low-κ material provides isolation. This localized functional differentiation enables multi-threshold voltage control in FinFETs without requiring complex work function layer engineering.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If dipole layer thickness is increased to achieve greater Vt shift, then work function tuning improves, but equivalent oxide thickness increases

Engineering Contradiction:
ImproveVt tuning rangeVSAvoidequivalent oxide thickness
Core Design Contradiction:
Adaptability or versatilityVSLength of stationary object

Solution Approach 1:

The patent employs composite dielectric materials consisting of high-κ and low-κ layers. The high-κ material provides enhanced capacitance and strong electric field control for effective threshold voltage tuning, while the low-κ material contributes to electrical isolation. This composite structure achieves the desired Vt shift range without increasing the equivalent oxide thickness, as the high-κ layer's superior dielectric constant compensates for reduced physical thickness.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for improved Vt tuning and multi-Vt adjustments without increasing EOT, simplifying the integration process and reducing the need for extreme p-type work function materials, thereby enhancing the performance and reliability of FinFET devices.

Implementation Method 1

depositing a high-κ dielectric material on the interlayer dielectric

Methodology Applied
Scientific EffectDielectric effect: Dielectric

Implementation Method 2

depositing a dipole layer on the high-κ dielectric material

Methodology Applied
Scientific EffectDipole effect:

Data Source

PatentUS11996455B2P-type dipole for P-FET
Publication Date: 2024.05.28 APPLIED MATERIALS INC
  • US11996455B2 patent drawing
  • US11996455B2 patent drawing
  • US11996455B2 patent drawing

AI summary

Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-κ dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).