pFET Nonvolatile Memory Cell With Control Capacitor
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Solution Overview
Problem
Existing nonvolatile memory technologies face challenges in efficiently storing and retrieving data in RFID tags and similar devices without a power supply, particularly in reducing write disturb and achieving reliable data retention with simpler fabrication processes.
Innovation Solution
The use of floating-gate p-channel field effect transistors (pFETs) with control capacitors and specific voltage biasing schemes to manage electron charge on floating gates, allowing for efficient read/write operations and reducing write disturb through optimized signal line control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nonvolatile memory structures are used, then data storage capability is achieved, but write disturb increases and fabrication complexity increases
Solution Approach 1:
The memory cell is segmented into distinct functional regions: a first pFET for read operations, a second pFET for write operations, and a control capacitor for charge storage. This segmentation allows independent optimization of read and write paths, reducing write disturb to stored data while maintaining reliable data retention through separate control mechanisms for each transistor.
2Reliability
If complex memory structures are used to improve data retention, then reliability improves, but device complexity increases
Solution Approach 1:
The control capacitor serves multiple functions: it stores data charge during write operations, maintains voltage during read operations, and enables both read and write functionality through a single shared component. The first and second pFETs share common structure elements and control signals, reducing overall device complexity while achieving reliable data retention through multi-functional operation.
3Ease of manufacture
If standard CMOS processes are used for fabrication, then manufacturing cost decreases, but manufacturing precision for floating gate structures increases
Solution Approach 1:
The invention uses parameter changes in the form of controlled voltage biasing schemes during fabrication to achieve precise floating gate charge distribution. By adjusting voltage parameters during the formation process, the patent achieves the required manufacturing precision for floating gate structures while remaining compatible with standard CMOS processes, thus maintaining cost-effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable data storage and retrieval in RFID tags and other devices with improved data retention and reduced write disturb, utilizing standard logic CMOS processes for cost-effective fabrication and efficient data management.
Implementation Method 1
a first floating gate coupled to the first MOS transistor and the first control capacitor
Implementation Method 2
floating-gate p-channel field effect transistors (pFETs) to store information as electric charge
Data Source
AI summary
A non-volatile memory integrated circuit includes multiple memory cells, each memory cell including a first MOS transistor, a first control capacitor, and a first floating gate coupled to the first MOS transistor and the first control capacitor. A first read/write control signal is provided having at least a first state and a second state and coupled the first MOS transistor. When the control signal is in the first state, the memory cell is configured for readout, and when the control signal is in the second state, the memory cell is configured for writing. Both single-ended and differential memory cells are described. Arrays of such nonvolatile memory cells are also described.