P-channel FET Fabrication with Pre-amorphization and Co-implantation
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Solution Overview
Problem
As transistors are miniaturized, short-channel effects become significant, and existing ultra-shallow junction formation techniques, such as co-implantation and epitaxial growth using silicon germanium, face limitations in controlling junction depth and reducing current leakage, while also causing diffusion issues that exacerbate short-channel effects.
Innovation Solution
A fabrication method for p-type channel field-effect transistors involving pre-amorphization implantation, pocket implantation, and multiple co-implantation processes with species like carbon or fluorine to define source/drain region depth profiles, combined with epitaxy growth to form semiconductor compound layers, mitigates short-channel effects and enhances transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor size is reduced to achieve high speed and low power consumption, then transistor saturation drain current and gate capacitance are improved, but short-channel effects become significant causing current leakage and reduced device reliability
Solution Approach 1:
The patent applies pre-amorphization implantation before dopant implantation to modify the substrate structure in advance. This preliminary action creates a controlled amorphous layer that prevents unwanted dopant diffusion during subsequent processing, thereby maintaining junction integrity and reducing short-channel effects in miniaturized transistors
Solution Approach 2:
The patent employs multiple co-implantation species (carbon, fluorine, silicon) with carefully controlled implantation energies and sequences. By changing the physical and chemical parameters of the implanted species and their implantation conditions, the patent achieves precise control over junction depth and dopant distribution, mitigating short-channel effects while maintaining high-speed performance
2Manufacturing precision
If co-implantation with carbon ions is used to increase saturation voltage and control short-channel effects, then junction depth profile becomes abrupt, but high electric field is induced causing serious current leakage
Solution Approach 1:
The patent uses composite implantation schemes combining multiple species (carbon, fluorine, silicon) in specific sequences. The fluorine ions moderate the electric field effects caused by carbon ions, while silicon ions provide additional junction control. This composite approach achieves abrupt junction profiles without inducing excessive electric fields that would cause current leakage
Solution Approach 2:
The patent introduces fluorine ions as an intermediary species between carbon and silicon implantation. The fluorine acts as a mediator that controls the interaction between carbon and silicon atoms during diffusion, preventing the formation of high electric field regions while maintaining precise junction depth control
3Speed
If epitaxial growth is used to form silicon germanium source/drain region to enhance carrier mobility, then electron and hole mobility are improved, but high temperature causes boron diffusion leading to short-channel effects
Solution Approach 1:
The patent performs pre-amorphization implantation and multiple co-implantation processes before epitaxial growth to establish precise dopant distributions and junction profiles. This preliminary preparation ensures that subsequent high-temperature epitaxial growth does not cause excessive boron diffusion, as the junction structures are already stabilized
Solution Approach 2:
The patent divides the source/drain formation into multiple stages: pre-amorphization implantation, multiple co-implantation processes with different species, and finally epitaxial growth. This segmentation allows each process to be optimized independently, achieving both high carrier mobility and precise junction control without the drawbacks of single-step approaches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces transient enhanced diffusion of boron ions, improves junction control, and enhances electron mobility, thereby mitigating short-channel effects and current leakage, leading to improved transistor performance and reliability.
Implementation Method 1
performing a pre-amorphization implantation (PAI) process to amorphize the substrate at both sides of the gate structure; performing a pocket implantation process to form an N-type pocket region in the substrate; performing a first co-implantation to define a P-type source/drain extension region depth profile
Implementation Method 2
forming a semiconductor compound layer in the substrate beside two sides of the gate structure and forming a P-type source/drain region in the semiconductor compound layer
Data Source
AI summary
A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.