FinFET pFET Threshold Voltage via SiGe Sidewall Strain
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Solution Overview
Problem
Conventional high dielectric constant (high-K) metal gate fin field effect transistors (FETs) face challenges in achieving a target threshold voltage for p-type FETs without compromising device performance, as growing a thin layer on fin sidewalls increases fin width, degrading electrostatics and making it difficult to maintain acceptable dimensions for advanced nodes.
Innovation Solution
The method involves forming fin structures in a semiconductor material, epitaxially depositing a donor material like Silicon-Germanium (SiGe) on the sidewalls, applying a condensation process to integrate the donor material into the semiconductor, and removing it to create a strained SiGe fin for p-type FETs, while maintaining the same width dimension as silicon fins for n-type FETs, thus achieving comparable threshold voltages and improved pFET performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin layer is grown on fin sidewalls to lower pFET threshold voltage, then the threshold voltage is improved, but the fin width increases, degrading electrostatics
Solution Approach 1:
The patent applies different materials (SiGe vs Si) to different fin structures based on their intended function (pFET vs nFET). The SiGe material is selectively deposited on fins designated for pFETs, while Si fins are used for nFETs. This local differentiation allows threshold voltage tuning for pFETs without affecting nFET dimensions or performance.
Solution Approach 2:
The patent segments the fin structures into two distinct groups: SiGe fins for pFETs and Si fins for nFETs. This segmentation is achieved through selective masking and epitaxial growth processes that treat different fin regions differently, enabling independent optimization of each transistor type's electrical characteristics.
2Reliability
If donor material is epitaxially deposited on fin sidewalls to induce strain, then pFET performance is improved, but the process complexity increases
Solution Approach 1:
The patent combines multiple functions into a single epitaxial growth step: (1) selective deposition of SiGe on pFET fins, (2) strain induction in the silicon lattice, and (3) threshold voltage tuning. By merging these functions into one process step, the patent reduces overall process complexity compared to sequential operations.
Solution Approach 2:
The SiGe material acts as an intermediary that introduces strain into the silicon lattice without requiring direct modification of the silicon structure. The SiGe layer serves as a mediator that transfers mechanical strain to the channel region, improving carrier mobility and threshold voltage characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the attainment of target threshold voltages for both n-type and p-type FETs, maintaining dimensional accuracy and enhancing pFET performance through strain relaxation, which is beneficial for integrated circuit components like logic gates.
Implementation Method 1
applying a condensation process to move the donor material through the sidewalls into the semiconductor material
Implementation Method 2
A donor material is epitaxially deposited on the exposed sidewalls of the fin structures
Implementation Method 3
enhancing pFET performance through strain relaxation
Data Source
AI summary
A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.