PFET Strain Relaxation via Segmented Stress Engineering
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Solution Overview
Problem
Strain relaxation in PFET devices reduces device performance due to the loss of desired stress in the channel region, which is particularly acute for PFET transistors, impacting the electrical performance of integrated circuit products.
Innovation Solution
The formation of first and second spaced-apart P-active regions with varying lengths and numbers of PFET transistors, where a tensile-stressed layer is applied to the first PFET transistor and a compressive-stressed layer is applied to the second PFET transistors, to maintain and enhance stress profiles in the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a layer of compressive-stressed material is formed above PFET transistors to impart compressive stress in the channel region, then device performance is improved, but the desired stress level significantly decreases after formation of the initial stressed layer
Solution Approach 1:
The patent divides the PFET transistor structures into different groups (first PFET transistors with shorter channel length and second PFET transistors with longer channel length) and applies different stress engineering approaches to each group. This segmentation allows optimization of stress maintenance for each transistor type, preventing strain relaxation in both short-channel and long-channel devices.
Solution Approach 2:
The patent applies different stress conditions to different regions: tensile stress is applied to the first PFET transistors (shorter channel) while compressive stress is applied to the second PFET transistors (longer channel). This local differentiation ensures that each region receives the appropriate stress type and magnitude to maintain desired stress levels and prevent relaxation.
2Speed
If the gate length is scaled down to 20-50 nm to increase operating speed, then device speed is improved, but strain relaxation becomes more pronounced
Solution Approach 1:
The patent implements preliminary stress engineering measures during the transistor fabrication process, forming stressor layers and configuring device structures in advance to establish and maintain the desired stress state in the channel region before the device is put into operation. This preliminary action ensures that stress is properly established at the nanoscale dimensions.
Solution Approach 2:
The patent changes key parameters including channel length (L), width (W), and the dimensions of stressor regions (L1, W1, L2, W2) to optimize stress distribution. By adjusting these geometric parameters, the patent maintains effective stress levels in scaled-down devices where strain relaxation would otherwise be pronounced.
3Adaptability or versatility
If selective formation of stressed material layers is performed by masking and blanket-deposition, then stress can be applied to specific transistor types, but the process complexity increases
Solution Approach 1:
The patent segments the transistor array into distinct regions (first and second P-active regions) with different dimensions and stress requirements. This structural segmentation enables selective stress application through straightforward processing techniques, reducing the need for complex masking and re-masking operations while still achieving type-specific stress engineering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach helps maintain or improve the desired stress levels in PFET transistors, enhancing their performance and reducing strain relaxation, thereby improving the overall electrical performance of integrated circuit products.
Implementation Method 1
a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region
Data Source
AI summary
One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.