PG Pin Pull-Up Resistance Checks for VR Power-On Timing
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Solution Overview
Problem
Existing VR chips face issues with determining the properness of the power-on timing sequence of PG pins, leading to potential incorrect actions in subsequent circuits due to abnormal PG signal behavior, particularly caused by improper pull-up resistor values.
Innovation Solution
A method and system for detecting the properness of the PG pin power-on timing sequence by determining the actual resistance of the pull-up resistor, comparing it to predefined resistance values based on maximum withstand current, edge rates, and interference voltage limits, and outputting prompt information when the resistance is improper to prevent incorrect actions in subsequent circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pull-up resistor is used to achieve high-level signal output for the PG signal, then the PG signal can be properly output, but the resistance value may be improper causing the PG pin power-on timing sequence to have hidden dangers
Solution Approach 1:
The patent performs preliminary detection of the pull-up resistor resistance value before system operation by measuring the actual resistance and comparing it against predefined threshold values. This preliminary action identifies improper resistance values before they can cause timing sequence errors, allowing for early correction or warning without affecting subsequent system reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the detected actual resistance value is compared with threshold values, and prompt information is output when the resistance is improper. This feedback loop ensures that the pull-up resistor configuration is continuously monitored and validated, maintaining manufacturing precision requirements throughout system operation.
2Ease of operation
If the PG signal is used as an Enable signal for subsequent circuits, then power-on timing control is achieved, but abnormal PG signal behavior causes incorrect actions in subsequent circuits
Solution Approach 1:
The patent detects and validates the PG pin power-on timing sequence before the subsequent circuits are activated. By performing this detection in advance, the system ensures that the PG signal will properly control the power-on timing of subsequent circuits, preventing incorrect actions before they occur.
Solution Approach 2:
The patent introduces an intermediary detection mechanism that monitors the PG signal behavior and pull-up resistor characteristics. This intermediary layer validates the timing sequence integrity before it reaches the subsequent circuits, acting as a buffer that prevents abnormal PG signal behavior from causing incorrect actions in the downstream circuits.
3Device complexity
If the actual resistance of the pull-up resistor is not detected, then the detection system remains simple, but the power-on timing sequence properness cannot be determined
Solution Approach 1:
The patent employs a self-service detection approach where the system uses its own operational characteristics (current consumption at different voltage levels) to automatically measure the pull-up resistor resistance value. This method avoids requiring external specialized measurement equipment, maintaining detection system simplicity while achieving precise measurement of the timing sequence properness through the resistance value.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively determines whether the power-on timing sequence of PG pins in VR chips is proper, preventing incorrect actions in subsequent circuits by ensuring the pull-up resistor values meet specific criteria, thus ensuring safe and reliable power supply.
Implementation Method 1
determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip
Implementation Method 2
obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value
Data Source
AI summary
A method, system, and related component for detecting properness of a PG pin power-on timing sequence are provided. The method comprises: obtaining a pull-up level of a PG pin of a VR chip (S101); determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip (S102); obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value (S103); and outputting first prompt information when it is determined that an actual resistance of the pull-up resistor is lower than the first resistance or the second resistance (S104). The foregoing solution is applied, to determine whether a power-on timing sequence of PG pins in a VR chip is proper, thereby avoiding an incorrect action of a subsequent circuit.