p-GaN GaN Power Structure for Current Collapse Suppression
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Solution Overview
Problem
Gallium nitride (GaN) power devices experience on-resistance degradation due to the current collapse effect, which affects dynamic stability and conduction characteristics, and existing solutions complicate the manufacturing process and reduce device reliability.
Innovation Solution
A GaN power device structure featuring a substrate, buffer, GaN channel, and barrier layers with a p-GaN cap and thin layer on the barrier layer, where the p-GaN thin layer is connected to the p-GaN cap and positioned between input and output electrodes, effectively shielding surface traps and enhancing hole injection to suppress current collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an additional layer of p-GaN structure is introduced through selective etching to suppress current collapse, then current collapse suppression is improved, but device structure complexity increases and manufacturing process becomes more complicated
Solution Approach 1:
The patent segments the barrier layer into two distinct regions: a gate region with a first thickness and a drain region with a second thickness (different from the first). This segmentation allows different functional optimization in different regions - the gate region maintains sufficient barrier thickness for proper transistor operation, while the drain region has reduced thickness to suppress current collapse, thereby resolving the contradiction between reliability improvement and structural complexity.
2Ease of operation
If the barrier layer is completely etched away in the gate region to enhance mode operation, then enhancement mode is achieved, but channel layer is exposed to etching gas causing damage and defects that reduce two-dimensional electron gas mobility
Solution Approach 1:
The patent applies local quality by giving the barrier layer different thicknesses in different regions. The gate region maintains a first thickness that protects the channel layer from etching damage while still enabling enhancement mode operation, whereas the drain region has a second thickness optimized for current collapse suppression. This localized differentiation resolves the contradiction between achieving enhancement mode operation and preserving channel layer integrity.
3Reliability
If a p-GaN cap layer and p-GaN thin layer structure is adopted, then current collapse suppression is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming the different thickness regions of the barrier layer during the epitaxial growth process itself, before subsequent device fabrication steps. The barrier layer is grown with spatially varying thickness (first thickness in gate region, second thickness in drain region) in a single continuous process, which prevents the need for complex post-growth etching and re-growth operations, thereby reducing manufacturing precision requirements while achieving current collapse suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively suppresses current collapse by weakening surface trap effects and improving dynamic conduction characteristics, enhancing the reliability and stability of GaN power devices.
Implementation Method 1
the shielding effect of the p-GaN thin layer on the surface traps is configured to weaken the effect of the surface traps on the barrier layer
Implementation Method 2
the hole injection effect achieved through the p-GaN cap layer and p-GaN thin layer can effectively suppress the current collapse effect caused by buffer layer traps
Implementation Method 3
a barrier layer; wherein the buffer layer, the GaN channel layer and the barrier layer are stacked sequentially from bottom to top on the substrate
Data Source
AI summary
Disclosed are a GaN power device and a manufacturing method thereof. The GaN power device includes a substrate, and a buffer layer, a GaN channel layer and a barrier layer sequentially stacked on the substrate from bottom to top. The barrier layer is provided with a p-GaN cap layer and a p-GaN thin layer, and the p-GaN thin layer is configured to cover the surface of the barrier layer and is connected to the p-GaN cap layer; the upper surface of the barrier layer is also provided with an input electrode and an output electrode, and a control electrode is provided on the upper surface of the p-GaN cap layer. The control electrode and the p-GaN thin layer are located between the input electrode and the output electrode.