pGaN HEMT Gate Sealing and Passivation for Low On-Resistance
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Solution Overview
Problem
Existing AlGaN/GaN HEMT devices face challenges in achieving enhancement mode operation while maintaining low on-resistance and high threshold voltage due to etching processes that damage the barrier layer, leading to a trade-off between on-resistance, pinch-off voltage, and gate current.
Innovation Solution
The HEMT device incorporates a gate region with a channel modulating pGaN layer and an interlayer region of TiN, along with a passivation layer of AlN, which optimizes the 2DEG densities and sheet resistance, allowing for a high threshold voltage and low on-resistance through tailored sealing and passivation layer parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching processes are used to form gate region, then device fabrication is enabled, but barrier layer is damaged causing increased sheet resistance and on-resistance
Solution Approach 1:
The gate region is divided into multiple segments along the channel direction, with each segment separated by recesses. This segmentation allows selective etching that removes damaged barrier layer portions while preserving intact barrier layer regions, thereby reducing overall on-resistance while maintaining fabrication feasibility.
Solution Approach 2:
Instead of attempting to protect the barrier layer during etching, the invention inverts the approach by intentionally removing damaged barrier layer portions through selective etching in recessed regions. This transforms the etching process from a harmful operation to a beneficial one that eliminates resistance-causing defects.
2Manufacturing precision
If barrier layer parameters are changed to reduce on-resistance, then on-resistance decreases, but pinch-off voltage and threshold voltage are reduced
Solution Approach 1:
The barrier layer is designed with non-uniform properties along the channel direction. In recessed regions, the barrier layer is selectively removed or thinned to reduce resistance, while in active channel regions, the barrier layer maintains its original thickness and composition to preserve high pinch-off voltage and threshold voltage characteristics.
Solution Approach 2:
The invention changes the barrier layer parameters (thickness, composition) in specific localized regions rather than uniformly across the entire device. By reducing barrier layer thickness or altering composition only in recessed areas, the sheet resistance is reduced without affecting the pinch-off voltage determined by the barrier layer in active channel regions.
3Reliability
If enhancement mode operation is achieved, then safe operation and circuit drive simplification are obtained, but on-resistance increases due to etching damage
Solution Approach 1:
The recessed regions act as intermediary zones between the gate electrode and the active channel. These recesses provide a transition area where damaged barrier layer is removed, creating low-resistance paths that mediate between the enhancement mode operation requirement and the need for low on-resistance performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a good trade-off between gate current, threshold voltage, and on-resistance, while also reconstructing potential defects in the barrier layer, resulting in improved electrical performance and reduced interface state density.
Implementation Method 1
a semiconductive heterostructure (based generally on AlGaN/GaN layers) allows a so-called 2-dimensional electron gas (2DEG) to be spontaneously generated in the device, thereby forming a channel path for electrical charges
Implementation Method 2
The spontaneous channel may be modulated by applying suitable voltages at a gate region, over the channel path
Data Source
AI summary
A HEMT transistor has a body having a top surface and a heterostructure, and a gate region having a semiconductor material and arranged on the top surface of the body. The gate region has a first lateral sidewall and a second lateral sidewall opposite to the first lateral sidewall. The HEMT device further has a sealing layer of non-conductive material that extends on and in contact with the first and the second lateral sidewalls of the gate region; and a passivation layer of non-conductive material that has a surface portion. The surface portion extends on the top surface of the body, laterally to the first lateral sidewall of the gate region. The sealing layer and the passivation layer have different geometrical parameters and/or are of different material.