pGaN HEMT Gate Protection for Monolithic D-Mode and E-Mode Integration
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Solution Overview
Problem
Current manufacturing processes for High Electron Mobility Transistor (HEMT) devices cannot integrate depletion mode (D-mode) and enhancement mode (E-mode) HEMTs with pGaN-gate structures in a monolithic and high-performance manner, as etching during D-mode manufacturing damages the barrier layer, leading to degraded electrical performance and separate assembly is required.
Innovation Solution
A HEMT device with a dielectric protection layer thinner than 10 nm, interposed between the barrier layer and the gate region, which prevents etching damage and allows integration of D-mode and E-mode HEMTs, maintaining high electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etching is used to form the gate structure of D-mode HEMT, then the Schottky contact can be formed, but the barrier layer is damaged and electrical performance is degraded
Solution Approach 1:
A thin dielectric protection layer (5-10 nm) is introduced as an intermediary between the barrier layer and the metal gate region. This layer allows the gate structure to be formed without direct contact between the metal and barrier layer, preventing damage while enabling Schottky contact formation. The dielectric layer acts as a protective mediator that eliminates the harmful etching effect on the barrier layer.
Solution Approach 2:
The dielectric protection layer is deposited on the barrier layer before forming the metal gate region. This preliminary protective action prevents subsequent etching processes from damaging the barrier layer, allowing the gate structure to be formed safely without compromising the underlying barrier layer integrity.
2Ease of manufacture
If D-mode HEMT with Schottky gate is manufactured separately from E-mode HEMT, then manufacturing complexity is reduced, but device integration and assembly complexity increase
Solution Approach 1:
The dielectric protection layer structure serves multiple functions: it protects the barrier layer during gate formation, enables both D-mode and E-mode HEMT manufacturing using the same process flow, and allows monolithic integration of different HEMT modes on the same substrate. This universal approach eliminates the need for separate assembly processes.
Solution Approach 2:
The manufacturing processes for D-mode and E-mode HEMTs are merged into a single integrated process flow. Both device types can now be fabricated simultaneously on the same substrate using the same dielectric protection layer technique, combining previously separate manufacturing operations into one unified process.
3Object-affected harmful factors
If thicker dielectric protection layer is used, then barrier layer protection is improved, but manufacturing precision and electrical performance are degraded
Solution Approach 1:
The thickness of the dielectric protection layer is precisely controlled within the range of 5-10 nm. This parameter optimization provides sufficient protection to the barrier layer during manufacturing while maintaining the electrical performance requirements. The specific thickness range balances protection needs with electrical characteristics, preventing both under-protection and over-protection issues.
Data Source
AI summary
HEMT device comprising: a heterostructure comprising a channel layer and a barrier layer extending, along a first axis, onto the channel layer; a dielectric protection layer of dielectric material, extending along the first axis onto the barrier layer; and a gate region extending along the first axis onto the dielectric protection layer, wherein the dielectric protection layer has, along the first axis, a thickness lower than 10 nm.