pGaN HEMT Gate-Passivation Spacing for Lower Gate Leakage
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Solution Overview
Problem
High electron mobility transistors (HEMTs) face challenges with gate leakage, particularly due to etching processes that create defects and electronic surface states in pGaN layers, leading to shifts in threshold voltage and increased on-resistance, which existing surface passivation methods fail to adequately address.
Innovation Solution
The introduction of spacer regions made of dielectric material between the gate metal region and the passivation layer in HEMT devices, which separates the gate metal from the passivation layer and prevents current leakage along the sidewalls, forcing the gate current to flow only at the Schottky contact, thereby reducing lateral gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If surface passivation is applied to reduce gate leakage, then gate leakage is reduced, but manufacturing complexity increases
Solution Approach 1:
The gate structure is segmented into multiple functional regions: a gate metal region, a first insulating layer, and a second insulating layer with an opening. This segmentation allows each layer to perform its specific function (conduction, insulation, and controlled exposure) thereby reducing gate leakage through the insulating layers while maintaining manufacturability through standardized layer-by-layer fabrication processes
Solution Approach 2:
The first insulating layer acts as an intermediary between the gate metal region and the second insulating layer. This intermediate insulating layer provides an additional barrier against gate leakage while the opening in the second insulating layer allows for selective electrical contact, thereby reducing overall gate leakage without requiring complete coverage that would increase manufacturing complexity
2Ease of manufacture
If etching processes are used to form gate structures, then device fabrication is enabled, but defects and electronic surface states are created in pGaN layers
Solution Approach 1:
The gate metal region and first insulating layer are formed before the second insulating layer is deposited. This preliminary formation of the gate structure allows subsequent layers to be deposited over it without requiring additional etching of the pGaN layer, thereby enabling device fabrication while preserving the quality of the pGaN layer by avoiding further etching damage
Solution Approach 2:
The first insulating layer serves as a cushioning layer that protects the pGaN layer from damage during subsequent processing steps. By placing this protective insulating layer beforehand, the pGaN layer is shielded from potential etching damage and surface state generation that would occur if further etching were performed
3Ease of manufacture
If gate metal is placed in direct contact with passivation layer, then manufacturing is simplified, but lateral gate leakage increases
Solution Approach 1:
The first insulating layer acts as an intermediary between the gate metal region and the second insulating layer, preventing direct contact between conductive and insulating materials. This intermediate layer blocks lateral gate leakage paths while the opening in the second insulating layer allows for necessary electrical contact, thereby reducing gate leakage without significantly complicating the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a good trade-off between gate current, threshold voltage, and on-resistance, improving the overall performance of HEMT devices by minimizing parasitic gate leakage and maintaining optimal electrical characteristics.
Implementation Method 1
a passivation layer (58; 58′) of non-conductive material, extending on the semiconductor body (52), partially on the top surface of the control region (57; 57′) and on the lateral sides of the control region (57; 57′)
Implementation Method 2
forcing the gate current to flow only at the Schottky contact
Data Source
AI summary
An HEMT device is formed on a semiconductor body having a semiconductive heterostructure. A control region of a semiconductor material, is arranged on the semiconductor body and has a top surface and lateral sides. A control terminal, of conductive material, extends on and in contact with the top surface of the control region. A passivation layer of non-conductive material, extends on the semiconductor body, partially on the top surface of the control region and on the lateral sides of the control region, laterally and at a distance from the control terminal.