Patterned Ground Shielding for Inductor Parasitic Capacitance
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Solution Overview
Problem
Traditional shielding structures on integrated circuits (ICs) lead to unwanted parasitic capacitance, which degrades the performance of inductors and other devices, especially as the scaling down process continues, due to the close proximity of conductive plates.
Innovation Solution
Implementing a patterned ground shielding (PGS) structure on a separate die with a significant underfill layer, where the shielding structure is formed with meandrous segments in different layers and misaligned to increase the distance between the inductor and shielding, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a traditional shielding structure is implemented on the IC chip, then isolation for devices such as inductors is provided to reduce the harmful effects of noise and interference, but unwanted parasitic capacitance is generated which lowers the quality factor of devices and degrades their performance
Solution Approach 1:
The shielding structure is extracted from the same die as the inductor and placed on a separate second die. This physical separation removes the source of parasitic capacitance from proximity to the inductor, thereby maintaining noise shielding benefits while eliminating the harmful capacitive coupling that degrades inductor quality factor.
Solution Approach 2:
An underfill layer acts as an intermediary between the first die (containing the inductor) and the second die (containing the shielding structure). This intermediate layer provides electrical isolation and mechanical support, enabling the shielding structure to be positioned at an optimized distance that minimizes parasitic capacitance while maintaining effective electromagnetic interference shielding.
2Productivity
If the scaling down process continues to increase functional density, then more interconnected devices are packed per chip area, but the parasitic capacitance issue becomes exacerbated due to reduced spacing between components
Solution Approach 1:
The solution transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture. By placing the shielding structure on a separate die in the vertical dimension (stacked configuration), the design achieves effective shielding without increasing in-plane parasitic capacitance, thereby enabling continued scaling while maintaining signal integrity.
Solution Approach 2:
The integrated circuit system is segmented into separate functional dies: the first die contains the active devices (inductors) and the second die contains the shielding structure. This segmentation allows independent optimization of each die, enabling high functional density on the active die while placing the shielding function at a distance to minimize parasitic effects.
3Reliability
If the distance between the inductor and shielding structure is increased to reduce parasitic capacitance, then the quality factor improves, but the area occupied by the structure increases
Solution Approach 1:
The shielding structure is implemented as a patterned ground shield that can be positioned to overlap or align with the inductor footprint when viewed from above. This nesting approach allows the shielding function to be contained within or closely matched to the inductor's planar boundaries, minimizing the additional area occupied while maintaining sufficient vertical separation to reduce parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic capacitance, enhancing the quality factor and resonant frequency of inductors by increasing the distance between conductive plates and providing effective isolation against electromagnetic interference.
Implementation Method 1
a patterned ground shielding (PGS) structure disposed in a second interconnect structure of a second die separate from the first die. The PGS structure provides isolation for the inductor coil structure against electromagnetic interference
Implementation Method 2
Traditional shielding structures may still lead to unwanted parasitic capacitance, which can lower the quality factor of devices such as inductors and otherwise degrade their performance. The PGS structure is formed with meandrous segments in different layers and misaligned to increase the distance between the inductor and shielding, thereby reducing parasitic capacitance
Data Source
AI summary
The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.