Phantom IC Layout Density Views for IP-Safe Border Verification
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Solution Overview
Problem
The integration of intellectual property (IP) designs from vendors into semiconductor circuits often results in incomplete views for fabless semiconductor companies, leading to density gradient violations during manufacturability verification, causing project delays and increased costs.
Innovation Solution
A method is developed to generate a design density view database using layer density information as a proxy for actual layout design, allowing for the creation of a phantom design that includes boundary information without revealing physical layout details, enabling accurate representation of IP design densities without exposing proprietary data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the IP vendor provides only models of the IP design without the circuit layout database to protect intellectual property, then IP protection is improved, but the fabless semiconductor company has an incomplete view of the integrated circuit product at the borders of the IP design, leading to density gradient violations
Solution Approach 1:
The patent creates a phantom design that is a copy of the actual IP design layout, containing only the necessary density and geometric information for manufacturability verification. This copy provides the required information without revealing the actual proprietary design, thus protecting IP while enabling verification.
Solution Approach 2:
The phantom design acts as an intermediary between the IP vendor and the fabless semiconductor company. It mediates the information exchange by providing sufficient data for density verification while maintaining IP protection, allowing both parties to work effectively without direct access to sensitive layout information.
2Reliability
If the fabless semiconductor company uses models without physical layout information, then IP vendor's intellectual property is protected, but density gradient violations are likely to occur between the borders of the IP design and adjacent circuits
Solution Approach 1:
The phantom design creates a simplified copy of the IP design that includes density information and geometric shapes necessary for verifying manufacturability. This copy enables the fabless company to check for density gradient violations at IP design borders without accessing the actual proprietary layout.
Solution Approach 2:
The patent transforms the actual layout information into a phantom representation that changes the parameters from detailed geometric coordinates to density values and simplified geometric shapes. This parameter transformation maintains the essential information needed for density verification while protecting the original design.
3Manufacturing precision
If the semiconductor foundry verifies the merged design after tapeout, then manufacturing accuracy is improved, but project timeline is delayed due to detecting and addressing density gradient violations
Solution Approach 1:
The phantom design enables density verification to be performed in advance during the design phase, before tapeout. The fabless semiconductor company can identify and correct density gradient violations early by using the phantom design for verification, avoiding delays that would occur if verification were done only after tapeout by the foundry.
4Loss of information
If the IP vendor provides detailed layout information, then the fabless semiconductor company can perform complete verification, but intellectual property is exposed to theft
Solution Approach 1:
The patent creates a phantom design that is a simplified copy of the actual IP layout, containing only the density and geometric information necessary for verification. This copy provides complete verification capability for the fabless company while maintaining IP protection by not revealing the actual proprietary design details.
Solution Approach 2:
The patent extracts only the essential information needed for verification (density values, geometric shapes, boundary information) from the complete IP design layout. This extraction creates a phantom design that provides verification capability while leaving the proprietary design information protected and undisclosed.
Data Source
AI summary
Techniques for providing a representation of densities of layer material in an integrated circuit layout design without revealing actual layout design data to protect a vendor's proprietary design data are described. The representation of the density information is used to reduce or eliminate density violations at borders of distinct portions of the integrated circuit design. By exchanging standardized data in a density view database, the techniques described herein can be independent of the vendor. A method for manufacturing an integrated circuit includes generating a design density view database representing a first integrated circuit layout design by using layer density information associated with the first integrated circuit layout design as a proxy for actual layout design information.