Multiphase PWM Circuit With Phase Accumulation for High Resolution
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Solution Overview
Problem
Existing PWM signal generation methods face limitations in accuracy and resolution due to clock frequency constraints, particularly in high-frequency applications where precise control of duty cycle is necessary to minimize power consumption and noise levels.
Innovation Solution
A PWM signal generator circuit utilizing a multiphase clock generator to produce phase-shifted clock phases, allowing for precise control of switch-on and switch-off durations by combining these phases with adaptive clock switching and phase accumulation techniques, thereby enhancing resolution without increasing clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock frequency is increased to improve PWM signal accuracy and resolution, then the PWM signal precision is improved, but the switching losses increase
Solution Approach 1:
The patent divides the clock signal into multiple phase-shifted clock signals (e.g., 5 phases) using a delay-locked loop (DLL). Each phase is separated by a controlled delay period, allowing the PWM signal to be generated by selectively combining these phases rather than using a single high-frequency clock signal. This segmentation enables high-resolution PWM without requiring proportionally high clock frequencies, thus reducing switching losses while maintaining accuracy.
2Measurement precision
If the clock frequency is increased to improve PWM signal resolution, then the duty cycle control precision is improved, but the power consumption increases
Solution Approach 1:
The patent segments the clock period into multiple phase-shifted signals with controlled delays. By selecting and combining specific phases based on the desired duty cycle, the system achieves fine-grained control resolution without increasing the overall clock frequency. This allows precise duty cycle adjustment while maintaining lower power consumption compared to high-frequency clock approaches.
3Manufacturing precision
If multiple phase-shifted clock phases are used to improve PWM resolution, then the switching period accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent introduces a delay-locked loop (DLL) as an intermediary device that automatically generates and synchronizes multiple phase-shifted clock signals. The DLL includes delay elements and a feedback mechanism that ensures the phases are properly aligned and spaced. This intermediary structure manages the complexity of multiple phases by providing automatic synchronization and phase control, reducing the need for complex external timing circuitry.
Solution Approach 2:
The DLL incorporates a feedback mechanism where the output phases are monitored and adjusted to maintain proper phase relationships. This feedback ensures that the phase shifts remain accurate and consistent over time and temperature variations, maintaining switching period accuracy while using a standardized approach that doesn't require custom complex circuit design for each application.
4Measurement precision
If the switching frequency is increased to improve control resolution, then the output voltage precision is improved, but the noise levels increase
Solution Approach 1:
The patent segments the switching operation into multiple lower-frequency phases rather than using a single high-frequency switching signal. By distributing the switching action across multiple phase-shifted signals, the effective switching frequency is reduced for each individual switch, thereby reducing electromagnetic noise and EMI while maintaining high control resolution through the phased approach.
Data Source
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AI summary
A PWM signal generator circuit is described. The PWM signal generator circuit generates a PWM signal having a given switching duration comprising a switch-on duration and a switch-off duration. The PWM signal generator circuit comprising a multiphase clock generator configured to generate a given number n of phase-shifted clock phases (φ0...φn-1) having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit is configured to determine for each switch-on duration a first (k) and a second (l) integer number, and for each switch-off duration (TOFF) a third (p; i) and a fourth (q) integer number. The first integer number (k) is indicative of the integer number of clock periods of the switch-on duration and the second integer number (l) is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number (p; i) is indicative of the integer number (p) of clock periods of the switch-off duration or the integer number (i) of clock periods of the switching duration, and the fourth integer number (q) is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration. The PWM signal generator circuit comprises a clock switching circuit (100'), a timer circuit (102), a phase accumulator circuit (110') configured to generate a selection signal (SEL1) for the clock switching circuit (100') and a toggle circuit (114) configured to generate the PWM signal.