Digital Delay Lock Loop Control for Low-Latency Clock Alignment

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Solution Overview

Problem

Conventional delay lock loop (DLL) circuits in digital systems are susceptible to unwanted latencies due to characteristics of analog circuitry, particularly at higher frequencies and with smaller feature sizes, leading to errors and distortions in phase alignment between reference and output clock signals.

Innovation Solution

The implementation of digitally controlled DLL circuits that utilize a phase detector, phase accumulator, decoder, and delay element to align clock signals, combining digital and analog circuitry to mitigate latency and improve accuracy and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional analog DLL circuits are used, then the circuit can operate at basic frequencies, but unwanted latencies and errors occur at higher frequencies and smaller feature sizes

Engineering Contradiction:
Improveoperating frequencyVSAvoidphase alignment accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent replaces the conventional analog delay lock loop circuit with a digitally controlled delay lock loop circuit. The digital circuit uses digital signal processing instead of analog circuitry to achieve phase alignment, eliminating the unwanted latencies that plague analog implementations at high frequencies and small feature sizes.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operating parameters by using digital control words to precisely adjust delay elements. This allows for fine-grained control of phase alignment parameters, enabling accurate synchronization even at higher frequencies where analog circuits fail.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If analog circuitry is used in DLL circuits, then the implementation is simpler, but latency errors and distortions increase

Engineering Contradiction:
Improvecircuit implementation simplicityVSAvoidphase signal accuracy
Core Design Contradiction:
Ease of manufactureVSLoss of information

Solution Approach 1:

The patent substitutes digital circuitry for analog circuitry in the DLL implementation. While digital circuits may be slightly more complex to implement, they provide superior phase signal accuracy by eliminating the inherent latencies and distortions of analog components, particularly at high frequencies.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent uses digital copying and processing of phase information through digital signal paths. Instead of relying on analog signal integrity, the digital implementation copies and processes phase data through discrete digital elements, maintaining accuracy throughout the signal chain.

Inventive Principle:
Principle #26Copying

3Measurement precision

If digitally controlled DLL circuits are implemented, then phase alignment accuracy improves, but device complexity increases

Engineering Contradiction:
Improvephase alignment precisionVSAvoidcircuit structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the delay control function into multiple discrete delay elements that can be independently controlled by digital control words. This segmentation allows for precise phase alignment through digital programming while organizing the complexity into manageable, modular components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic control of delay elements through digitally programmable control words. The circuit can adapt its delay characteristics in real-time based on feedback from phase detectors, providing high precision phase alignment while managing complexity through adaptive digital control rather than fixed complex analog circuitry.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11211936B1Delay lock loop circuits and methods for operating same
Publication Date: 2021.12.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11211936B1 patent drawing
  • US11211936B1 patent drawing
  • US11211936B1 patent drawing

AI summary

Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.