Phase Accumulator Synchronization Without Synchronous SYSREF Transfer
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Solution Overview
Problem
Conventional methods for phase synchronization in high-speed digital systems face challenges in distributing synchronous SYSREF signals, leading to difficulties in synchronizing digital components due to tight setup and hold restrictions, especially at very-high-speed frequencies, which can disrupt downstream logic and prevent phase updates.
Innovation Solution
The system employs a local multiframe clock (LMFC) counter and a shadow phase accumulator to generate phase updates asynchronously, allowing phase synchronization without synchronous signal transfer by using a shadow counter to detect SYSREF pulses and transfer phase updates deterministically to the LMFC counter, even at high-speed PLL frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a synchronous SYSREF signal is distributed to multiple chips at high-speed PLL frequencies, then phase synchronization is achieved, but tight setup and hold restrictions make it difficult to distribute the signal synchronously throughout the IC
Solution Approach 1:
The patent divides the phase synchronization function into two independent counters: a first counter in the device clock domain and a second counter in the final digital clock domain. Each counter independently tracks phase information, eliminating the need for synchronous SYSREF signal distribution across the entire IC while maintaining phase synchronization accuracy.
Solution Approach 2:
The patent introduces a phase difference detection mechanism that acts as an intermediary between the two counters. This intermediary detects phase differences and generates update signals, allowing phase synchronization to be achieved without directly distributing the synchronous SYSREF signal throughout the IC.
2Reliability
If the high-speed clock output of the PLL is gated to prevent distribution beyond the gate, then downstream logic can be reset in clock-off mode, but further SYSREF-based phase updates are prevented without disturbing downstream logic
Solution Approach 1:
The patent moves the phase update mechanism to a different clock domain (final digital clock domain) rather than relying on the gated high-speed clock. The second counter operates independently in this dimension, allowing phase updates to occur without disturbing the gated downstream logic while maintaining adaptability for SYSREF-based phase updates.
3Measurement precision
If the SYSREF signal is used to reset the phase of counter-based components, then phase synchronization is achieved, but at cutting-edge frequencies it becomes difficult to distribute the SYSREF signal synchronously
Solution Approach 1:
The patent segments the phase reset function into two independent counters operating in different clock domains. The first counter handles phase tracking in the device clock domain, while the second counter handles phase updates in the final digital clock domain. This segmentation allows accurate phase resetting without requiring high-speed synchronous SYSREF signal distribution.
Data Source
AI summary
Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.