Phase Accumulator Synchronization Without Synchronous SYSREF Transfer
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Solution Overview
Problem
Conventional methods for phase synchronization in high-speed digital systems face challenges in distributing synchronous SYSREF signals, leading to difficulties in synchronizing digital components due to tight setup and hold restrictions, especially at very-high-speed frequencies, which can disrupt downstream logic and prevent phase updates.
Innovation Solution
The system employs a local multiframe clock (LMFC) counter and a shadow phase accumulator to generate phase updates asynchronously, allowing phase synchronization without synchronous signal transfer by using a shadow counter to detect SYSREF pulses and transfer phase updates deterministically to the LMFC counter, eliminating the need for synchronous signal distribution across high-speed domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous SYSREF signal is distributed to multiple chips in the system, then phase synchronization can be achieved, but it becomes difficult to distribute the SYSREF signal synchronously throughout the IC when the PLL is run at cutting-edge frequencies
Solution Approach 1:
The patent introduces an asynchronous phase update mechanism as an intermediary between the SYSREF signal and the downstream logic. Instead of directly distributing the synchronous SYSREF signal to all components, the system uses phase accumulation counters that can be updated asynchronously, allowing phase synchronization to be achieved without requiring synchronous signal distribution throughout the entire IC.
Solution Approach 2:
The patent replaces the mechanical/synchronous signal distribution system with an asynchronous digital processing system. By using phase accumulation counters and asynchronous updates, the system eliminates the need for precise synchronous signal distribution, substituting the traditional synchronous mechanism with a more flexible asynchronous digital approach.
2Reliability
If the high-speed clock output of the PLL is gated to prevent distribution beyond the gate, then downstream logic can be reset in clock-off mode, but this prevents further SYSREF-based phase updates without disturbing the downstream logic
Solution Approach 1:
The patent segments the phase synchronization function into separate components: a phase accumulation counter that can be updated asynchronously and the downstream logic that remains stable. This segmentation allows the phase update function to operate independently without disturbing the downstream logic, enabling both stability and adaptability.
Solution Approach 2:
The patent implements a dynamic system where the phase accumulation counter can be updated asynchronously based on SYSREF pulses even when the high-speed clock is gated. The system adapts its operation mode, allowing phase updates to proceed independently of the clock distribution state, thus maintaining both logic stability and update capability.
3Speed
If the PLL is run at cutting-edge frequencies for highest speed clocking, then system performance is improved, but it becomes difficult to distribute the SYSREF signal synchronously throughout the IC
Solution Approach 1:
The patent replaces the synchronous signal distribution mechanism with an asynchronous digital processing approach. By using phase accumulation counters that can be updated independently of the high-speed clock, the system achieves precise phase synchronization without requiring synchronous signal distribution, thus maintaining signal distribution precision even at cutting-edge frequencies.
Data Source
AI summary
Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.