Phase Acquisition Loop Reducing Preamble Length
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Solution Overview
Problem
Digital-synchronizing data-communications systems face limitations in data processing and storage due to slow phase-acquisition and gain-acquisition loops, which require long preambles, reducing the amount of data that can be processed or stored in a given time or storage medium.
Innovation Solution
The implementation of a phase-acquisition loop with a comparator, filter, and accumulator that reduces the number of preamble samples required to acquire phase-correction values, and a gain-acquisition loop with a digital VGA located behind the ADC, reducing latency and allowing for faster data processing and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase-acquisition loop is used to acquire phase difference between data and sample clock, then phase synchronization is achieved, but the acquisition process is slow and requires a long preamble
Solution Approach 1:
The patent applies preliminary action by using a zero-phase-restart (ZPR) circuit to generate an initial phase-correction value before the main phase-acquisition loop begins operation. This preliminary phase estimation allows the loop to start from a closer approximation of the correct phase, significantly reducing the number of iterations needed to achieve accurate phase synchronization and thereby shortening the required preamble length.
Solution Approach 2:
The patent replaces the conventional slow iterative phase-acquisition mechanism with a hybrid approach that incorporates a ZPR circuit performing preliminary phase calculation. This substitution of the pure iterative mechanical process with a pre-calculated initialization step accelerates the overall phase acquisition speed while maintaining accuracy.
2Measurement precision
If a conventional gain-acquisition loop with analog VGA before ADC is used, then gain control is achieved, but the loop is slow and requires long preamble for acquisition
Solution Approach 1:
The patent replaces the conventional analog VGA-based gain control system with a digital VGA implemented in the digital domain after the ADC. This substitution eliminates the need for slow analog gain adjustment during the preamble and allows for faster digital gain control, reducing the preamble length required for gain acquisition while maintaining or improving control precision.
Solution Approach 2:
The patent applies preliminary action by using a zero-gain-restart (ZGR) circuit to generate an initial gain-correction value before the main gain-acquisition loop begins. This preliminary gain estimation allows the digital VGA to start from a closer approximation of the correct gain level, reducing the number of iterations needed and thereby shortening the required preamble length.
3Reliability
If long preambles are used to accommodate slow acquisition loops, then adequate phase and gain acquisition is achieved, but the amount of data that can be processed or stored in a given time or storage medium is reduced
Solution Approach 1:
The patent applies preliminary action through ZPR and ZGR circuits that pre-calculate initial phase and gain correction values before the main acquisition loops operate. This preliminary initialization reduces the iteration time required for reliable acquisition, thereby shortening the preamble length and increasing the proportion of time available for actual data processing, thus improving overall productivity.
Solution Approach 2:
The patent replaces conventional analog gain control with digital VGA and accelerates phase acquisition through the ZPR initialization approach. These substitutions reduce the time required for reliable phase and gain acquisition, allowing more of the signal transmission time to be dedicated to actual data processing, thereby improving the data processing rate while maintaining acquisition reliability.
Data Source
AI summary
A phase-acquisition (PA) loop for a read channel comprises an accumulator, a comparator, and a filter. The accumulator holds an acquired phase-correction value corresponding to a difference between a phase of a sample clock and a phase of data carried by a read signal, and provides the acquired phase-correction value to a circuit that modifies the read signal to compensate for the phase difference. The comparator receives a reference phase-correction value that also corresponds to the difference between the phases of the sample clock and the data, and generates an error signal that is related to a difference between the reference and acquired phase-correction values. And the filter causes the acquired phase-correction value to have a predetermined relationship to the reference phase-correction value. Because such a PA loop may require significantly fewer samples of a read-signal preamble than prior PA loops requires to acquire the phase between a sample clock and data carried by a read signal, such a PA loop may allow one to significantly reduce the length of the preamble.