Phase-Aligned Clock Divider Circuit With Lower Power and Latency
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Solution Overview
Problem
High-speed networks and computer buses face challenges in maintaining signal integrity and transfer rates due to interconnect capacitance, which causes intersymbol interference and data corruption, and existing clock frequency dividers increase power consumption and latency.
Innovation Solution
The implementation of multiple clock frequency dividers at the I/O boundaries and across the die of an integrated circuit, utilizing a first and second clock divider with phase alignment or non-zero phase difference, and a combined multiplexer and flip-flop circuit to generate output clock signals with reduced frequency, allowing for efficient clock signal generation without synchronization circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional clock frequency dividers are used to generate output clock signals, then the frequency division function is achieved, but power consumption increases and latency increases
Solution Approach 1:
The patent combines the multiplexer and flip-flop into a single integrated circuit unit. The multiplexer selects between different clock signals while the flip-flop provides phase alignment, and their integration eliminates additional buffering and synchronization stages that would otherwise increase latency and power consumption. This merged architecture achieves frequency division while reducing both power consumption and latency compared to traditional separate implementations.
2Reliability
If multiple clock frequency dividers are implemented across the die, then signal integrity is maintained, but on-die area increases
Solution Approach 1:
The patent divides the integrated circuit into multiple segments, each containing a clock frequency divider with phase alignment capability. These segmented dividers are distributed across the die to maintain signal integrity over long interconnect distances. The segmentation allows each local segment to have its own synchronized clock source, reducing the need for long clock distribution networks and minimizing the total on-die area required for clock management while maintaining signal integrity.
3Stability of the object's composition
If phase alignment circuitry is added to clock dividers, then clock signal phase coherence is achieved, but device complexity increases
Solution Approach 1:
The patent merges the phase alignment function directly into the clock frequency divider circuit by integrating a flip-flop with the frequency division logic. This combined approach achieves phase coherence without requiring separate phase alignment circuitry, thereby avoiding additional complexity. The flip-flop is synchronized to the input clock and provides naturally aligned output phases, achieving phase coherence as an inherent feature rather than an added complexity.
Data Source
AI summary
A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.