Clock Selector Circuit for Phase-Aligned Oscillator Switching
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Solution Overview
Problem
Switching between clock signals from different oscillators, such as crystal and RC oscillators, is challenging due to phase misalignment, leading to switching artefacts and frequency shifts that can cause errors and are hard to debug, especially in battery-powered IoT devices where power efficiency and accuracy are critical.
Innovation Solution
A clock selector circuit with a phase difference detector and switching circuitry that aligns the phases of two input clock signals by detecting zero crossings and switching between them based on opposite edge detection, allowing seamless switching without a higher-frequency clock signal, thus minimizing interference and maintaining frequency tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching is performed directly between clock signals from different oscillators, then switching speed is improved, but phase misalignment causes switching artefacts and frequency shifts that lead to errors
Solution Approach 1:
The patent applies preliminary action by detecting the phase difference between clock signals from different oscillators before switching occurs. The phase difference detector continuously monitors the phase relationship and triggers the switch only when phase alignment is detected, preventing switching artefacts and frequency shifts that would otherwise cause errors in the clocked circuitry.
2Measurement precision
If a higher-frequency clock signal is used to coordinate switching, then switching precision is improved, but power consumption and design complexity increase
Solution Approach 1:
The patent applies self-service by using the clock signals themselves to detect phase difference and trigger the switching action. The phase difference detector utilizes the existing clock edges from the oscillators to determine when switching should occur, eliminating the need for an external higher-frequency reference clock and reducing both power consumption and design complexity while maintaining switching precision.
Data Source
AI summary
A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).