Phase Alignment Circuit Using Fractional Delay Calibration
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Solution Overview
Problem
Synchronizing communication between a memory controller and memory devices is challenging due to timing offsets between data and clock signals, especially at higher data rates, requiring precise timing calibration for each data signal across numerous memory devices.
Innovation Solution
A timing-calibration circuit is instantiated on an integrated circuit to produce phase-adjusted clock signals, utilizing a clock filter and fractional delay circuit to align signals precisely, minimizing power consumption by limiting the use of power-hungry circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If precise timing calibration is performed for each data signal across numerous memory devices, then synchronization accuracy is improved, but power consumption and area requirements increase significantly
Solution Approach 1:
The patent segments the timing calibration function by separating integer-delay calibration (performed once at system level) from fractional-delay calibration (performed selectively at individual device levels). This segmentation allows most devices to use the low-power integer calibration while only specific devices requiring higher precision engage the power-hungry fractional calibration circuits, thus resolving the contradiction between precision and power consumption.
Solution Approach 2:
The patent applies local quality by providing different calibration precision levels to different memory devices based on their specific requirements. Devices experiencing significant timing offsets receive full fractional-delay calibration, while others use standard integer-delay calibration. This selective approach ensures high precision where needed while minimizing power consumption across the overall system.
2Measurement precision
If precise timing calibration is performed for each data signal across numerous memory devices, then synchronization accuracy is improved, but area requirements increase significantly
Solution Approach 1:
The calibration system is segmented into two distinct functional blocks: an integer-delay calibration unit that covers the majority of timing adjustment needs, and a fractional-delay calibration unit that provides fine-grained adjustment only when necessary. This segmentation reduces the overall area by avoiding the need to instantiate full-precision calibration circuits at every memory device interface.
Solution Approach 2:
The patent implements partial calibration action by applying fractional-delay calibration only to the extent necessary for achieving synchronization, rather than over-calibrating all devices. This partial action approach reduces area requirements by activating complex calibration circuits only for specific devices that require them, while other devices use the simpler integer-delay calibration path.
Data Source
AI summary
A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements. The timing-calibration circuit minimizes system-wide power consumption by limiting the number and usage of active phase interpolators for delay adjustment in favor of the passive fractional delay elements.