Phase Alignment Between Skewed Clock Domains
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Solution Overview
Problem
Conventional solutions for aligning clock phases between different clock domains, such as PLL-based TXCDR and synchronous FIFO buffers, are either complex and power-consuming or introduce latency issues, making them unsuitable for low-latency applications.
Innovation Solution
An integrated circuit design that includes TX and RX circuitry with a pattern generator, multi-phase clock source, and clock multiplexer to align the RX clock signal with the TX clock signal by determining valid phase-shifted versions of the RX clock signal using a pattern checker and controller, eliminating the need for PLLs and FIFO buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL-based TXCDR is used to align clock phases, then phase alignment is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the essential function of phase alignment from the complex PLL circuit and implements it using a simplified multi-phase clock source with phase detectors and selective switching. This removes the unnecessary complexity of the PLL while retaining the core phase alignment capability.
Solution Approach 2:
The patent replaces the expensive, complex PLL circuit with simpler, less costly components including multi-phase clock sources, phase detectors, and multiplexers. These simpler components achieve the same phase alignment function without the high power consumption and complexity of PLLs.
2Reliability
If synchronous FIFO buffers are used to handle phase offset, then data transmission is accommodated, but transmission latency increases
Solution Approach 1:
The patent performs preliminary phase alignment by generating multiple phase-shifted clock signals in advance and selecting the appropriate phase before data transmission begins. This eliminates the need for FIFO buffers during operation, thereby avoiding the 1-2 cycle latency that FIFOs introduce.
Solution Approach 2:
The patent introduces phase detectors and a clock multiplexer as intermediaries between the TX and RX clock domains. These intermediaries enable direct phase-matched data transmission without requiring FIFO buffers, thus maintaining low latency while accommodating phase offsets.
3Reliability
If PLL circuit is used for phase alignment, then clock phase synchronization is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the high-power PLL circuit with lower-power alternatives including multi-phase clock sources and simple phase detectors. These components consume significantly less power while achieving the same clock phase synchronization function.
Solution Approach 2:
The patent extracts only the essential phase detection and selection functions from the PLL circuit, eliminating the high-power components while retaining the synchronization capability through a more energy-efficient architecture.
4Adaptability or versatility
If low-speed jittery clock is used to modify high-frequency macro PLL clock outputs, then clock flexibility is achieved, but system stability deteriorates
Solution Approach 1:
The patent implements dynamic phase selection where the system can adaptively choose from multiple pre-generated phase-shifted clock signals based on detected phase conditions. This provides flexibility without introducing jitter, as the phase selection is made from stable pre-generated signals rather than modifying a high-frequency clock with a low-speed clock.
Data Source
AI summary
In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.