Phase-Averaging PLL/DLL Clock Alignment for Multi-Tree Skew
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Solution Overview
Problem
Existing locked loop circuits, such as PLL and DLL, suffer from skew issues between input clocks and multiple clock tree outputs due to inherent design limitations, leading to incomplete phase alignment across different clock tree outputs.
Innovation Solution
The implementation of phase-averaging feedback clock circuitry within the PLL/DLL feedback path, which averages and aligns clock tree outputs to reduce skew by selecting and weighting signals from multiple clock trees, ensuring precise phase alignment with the input clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a feedback clock signal is derived from one clock tree output, then phase alignment with that specific clock tree is achieved, but skew remains with other clock tree outputs
Solution Approach 1:
The feedback clock signal is segmented into multiple components, each derived from different clock tree outputs. The phase detector processes each segment separately and combines the results to achieve comprehensive phase alignment across all clock trees, not just one.
Solution Approach 2:
Multiple feedback clock signals from different clock tree outputs are merged into a single composite feedback signal. This combined signal enables the phase detector to simultaneously consider phase relationships across all clock trees, achieving uniform phase alignment throughout the system.
2Manufacturing precision
If clock trees are designed to minimize skew, then manufacturing complexity increases, but incomplete phase alignment persists
Solution Approach 1:
A feedback mechanism is implemented where the phase detector continuously monitors phase differences between the reference clock and multiple clock tree outputs. The resulting control signal dynamically adjusts clock tree delays to maintain optimal phase alignment, compensating for manufacturing variations without requiring extremely precise initial design.
Solution Approach 2:
The clock tree delay elements are designed to be dynamically adjustable rather than fixed. This allows the system to adapt to actual phase relationships during operation, achieving precise alignment through dynamic control rather than static manufacturing precision.
3Measurement precision
If phase averaging feedback clock circuitry is implemented, then skew between input clock and clock tree outputs is reduced, but circuit complexity increases
Solution Approach 1:
Instead of perfectly balancing all phase relationships simultaneously, the system uses a simplified phase averaging approach that provides sufficient phase alignment for practical purposes. This partial action achieves acceptable skew reduction without requiring the full complexity of multiple independent feedback loops for each clock tree.
Solution Approach 2:
A phase averaging circuit is introduced as an intermediary between the multiple phase detectors and the delay control elements. This mediator combines multiple phase error signals into a single averaged control signal, simplifying the overall feedback architecture while maintaining effective phase alignment across all clock trees.
Data Source
AI summary
Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.