Phase-Averaging Clock Recovery for Low-Power Jitter Attenuation
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Solution Overview
Problem
Conventional PLL-based CDR circuits face challenges in managing jitter transfer and generation, where improving one aspect worsens the other, and phase-interpolator-based CDRs are power-consuming and unsuitable for low-power applications due to high frequency jitter issues and the need for multiple phase interpolators.
Innovation Solution
A phase-averaging CDR architecture that generates a clock signal without phase interpolators, using a digital block with a phase and frequency detector, charge pump, low-pass filter, voltage-controlled oscillator, and finite state machine to independently manage jitter transfer and generation, allowing for reduced power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL-based CDR circuits are used to improve jitter transfer performance, then low frequency jitter is attenuated, but high frequency jitter is passed and power consumption increases
Solution Approach 1:
The patent changes the operating parameters of the CDR circuit by using a wide-loop-bandwidth PLL configuration that operates effectively across a broad frequency range (e.g., 20 MHz to 20 GHz). This parameter change allows the circuit to achieve both low-frequency and high-frequency jitter attenuation without requiring multiple separate circuits, thereby reducing overall power consumption while maintaining reliable jitter transfer performance across the entire operating bandwidth.
2Reliability
If phase interpolators are added to CDR circuits to improve jitter attenuation, then jitter performance improves, but device area and power consumption increase
Solution Approach 1:
The patent extracts and removes the phase interpolator component from the CDR circuit architecture. By taking out this unnecessary component, the design achieves jitter attenuation performance without the associated penalties of increased device area and power consumption. The wide-loop-bandwidth PLL inherently provides the required jitter filtering functionality without requiring separate phase interpolation stages.
3Reliability
If multiple phase interpolators are used to cover different frequency ranges, then jitter transfer and generation are improved, but device complexity and area increase
Solution Approach 1:
The patent implements a universal CDR circuit design where a single wide-loop-bandwidth PLL configuration handles the entire frequency range (e.g., 20 MHz to 20 GHz) and manages both jitter transfer and generation across all operating conditions. This multi-functional approach eliminates the need for multiple specialized phase interpolators, thereby reducing device complexity while maintaining comprehensive jitter management capability across the full operating bandwidth.
Data Source
AI summary
In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.