Phase-Aware DDR Controller Scheduling for 1:4 Bus Utilization
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Solution Overview
Problem
Conventional DDR controllers face inefficiencies due to disparities in clock speeds between core and interface clocks, leading to coarser timing control granularity and reduced bus utilization in modes like 1:2 and 1:4, resulting in increased latency and decreased efficiency.
Innovation Solution
Implementing phase-aware control mechanisms, including phase-aware counters and state machines, which allow for sub-clock-cycle control granularity by partitioning core clock cycles into multiple phases, enabling finer control and signal detection equivalent to higher core clock speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the core clock speed is reduced to meet lower power consumption requirements, then power consumption is improved, but timing control granularity becomes coarser and latency increases
Solution Approach 1:
The patent divides a single core clock cycle into multiple phases (e.g., 4 phases in 1:4 mode), allowing the controller to perform multiple control operations within one clock cycle. This segmentation enables fine-grained timing control without requiring a higher core clock frequency, thus maintaining low power consumption while reducing access latency.
Solution Approach 2:
The patent introduces a phase dimension alongside the clock cycle dimension. By tracking and utilizing phase information within each clock cycle, the controller achieves sub-clock-cycle timing precision. This additional dimensional approach allows precise timing control without increasing clock frequency, thereby avoiding increased power consumption.
2Use of energy by moving object
If the core clock speed is reduced for lower power consumption, then power consumption is improved, but bus utilization decreases due to coarser control granularity
Solution Approach 1:
By segmenting the clock cycle into multiple phases and using phase-aware counters and state machines, the controller can manage multiple bus transactions more efficiently within the same time frame. This improves bus utilization by reducing idle periods and optimizing command scheduling, all while maintaining the lower core clock frequency for power efficiency.
Solution Approach 2:
The phase-aware controller performs preliminary actions by predicting optimal command issuance timing based on phase information. This allows the controller to proactively schedule commands to maximize bus utilization before actual data transfers occur, ensuring efficient bus usage without requiring higher clock speeds.
3Measurement precision
If counters are designed to count at core clock speed, then control precision is improved, but the system cannot achieve faster counting rates needed for high-frequency interface clocks
Solution Approach 1:
The patent implements phase-aware counters that count not only in terms of clock cycles but also in terms of phases within each cycle. This segmentation allows the counters to achieve effective counting rates that are multiples of the core clock frequency (e.g., 4x faster in 1:4 mode) while maintaining precise control, because each phase represents a discrete controllable unit.
Solution Approach 2:
The phase signal acts as an intermediary between the core clock and the interface clock. By using phase information as an intermediate measurement unit, the system achieves high-frequency timing precision without requiring the core clock itself to run at high frequencies. The phase counter effectively mediates between the low-speed core clock and the high-speed interface requirements.
4Device complexity
If the controller uses synchronous digital design with core clock, then design simplicity is improved, but timing control granularity becomes coarse when interface clock is much faster
Solution Approach 1:
The patent segments the timing control into two levels: coarse control at the clock cycle level (maintaining synchronous design simplicity) and fine control at the phase level (achieving sub-clock-cycle granularity). This hierarchical segmentation allows the design to retain the simplicity of synchronous digital design while adding fine-grained timing control capability through phase-aware elements.
Solution Approach 2:
The patent adds a phase dimension to the traditional clock-cycle-based synchronous design. By incorporating phase information as an additional control dimension, the system achieves fine timing granularity without abandoning the simplicity of synchronous design. The phase-aware state machines and counters extend the basic synchronous framework rather than replacing it.
Data Source
AI summary
Disclosed herein are system and electronic structure embodiments for implementing phase-aware control and scheduling. An embodiment includes a system with a bus controller configured to be activated in response to a first command. The bus controller may have a first clock speed and may drive an interface having a second clock speed. The system may further configure the bus controller to wait for a first time period in response to being activated, and a first circuit element structured to detect a first phase value of a first signal. In some embodiments, the bus controller may process a second command following passage of the first time period, and wait for a second time period, based on the detected first phase value and a ratio of the first and second clock speeds.