Phase Bar Insertion in IC Layout for Lithography Resolution
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces challenges in maintaining pattern fidelity and resolution during the scaling down process due to image distortion caused by resolution limitations in lithography, particularly in line-end features, which affects the complexity and efficiency of IC processing and manufacturing.
Innovation Solution
The method involves modifying the IC design layout by performing targeted-feature-surrounding checking, inserting phase-bars and scattering bars, and applying optical proximity correction to enhance image contrast and precision, thereby improving the lithography process through the use of phase-shifting masks and sub-resolution assist features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometric size is scaled down to increase functional density, then production efficiency increases and costs decrease, but image distortion and pattern fidelity deteriorate due to lithography resolution limitations
Solution Approach 1:
The patent applies optical proximity correction (OPC) techniques during mask fabrication to pre-compensate for anticipated lithography distortions. By calculating and adjusting pattern dimensions beforehand based on lithographic models, the method counteracts expected image distortion and line-end failures, ensuring accurate pattern transfer at scaled dimensions
Solution Approach 2:
The patent modifies mask pattern parameters such as line widths, spacing, and shapes to compensate for lithography resolution limitations. By adjusting these parameters during mask design and fabrication, the method optimizes pattern fidelity while maintaining scaled-down geometric dimensions for high functional density
2Quantity of substance
If geometric size is scaled down, then functional density increases, but image distortion increases causing line-end failures
Solution Approach 1:
The patent implements preliminary anti-action by applying OPC corrections to mask patterns before lithography. The method calculates expected distortions using lithographic models and pre-adjusts pattern geometries to counteract anticipated image distortion and line-end failures, thereby maintaining pattern fidelity at scaled dimensions
Solution Approach 2:
The patent employs iterative feedback loops where lithographic models predict pattern outcomes, corrections are applied to mask designs, and simulations verify improvements. This feedback mechanism continuously refines pattern parameters to minimize image distortion while maintaining high functional density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fidelity and resolution of IC patterns, improving the manufacturing process by reducing image distortion and increasing the complexity and efficiency of IC production, particularly at the line-end features, leading to better production efficiency and cost reduction.
Implementation Method 1
inserting phase-bars and scattering bars, and applying optical proximity correction to enhance image contrast and precision
Implementation Method 2
inserting phase-bars and scattering bars, and applying optical proximity correction to enhance image contrast and precision
Data Source
AI summary
A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.