Phase-Change Memory Arrays with Bipolar Selectors for In-Memory Convolution
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Solution Overview
Problem
Classical in-memory computation techniques using MOS transistors face scalability issues due to the need for large transistor sizes and reliability concerns with high intensity write currents, which affect the performance and reliability of resistive memory arrays.
Innovation Solution
Employing a phase-change memory cell array with bipolar transistors as selectors, utilizing time slots for voltage signal application and integrating read currents to perform convolutional computations, while compensating for temperature and process variations through calibration and offset voltage generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If MOS transistors are used as selectors in resistive memory arrays, then bidirectional current flow is enabled for programming, but transistor size must be large to drive high intensity write currents
Solution Approach 1:
The patent changes the transistor type from MOS to bipolar, fundamentally altering the electrical parameters. Bipolar transistors can drive high write currents with much smaller device dimensions due to their superior current density capabilities, resolving the contradiction between bidirectional current capability and transistor size
Solution Approach 2:
The patent substitutes MOS transistor technology with bipolar transistor technology. This replacement enables the same bidirectional current flow functionality for programming while achieving significantly reduced transistor footprint and improved scaling characteristics
2Area of moving object
If MOS transistors are scaled down to reduce size, then area is reduced, but reliability issues arise due to high intensity write currents
Solution Approach 1:
The patent replaces MOS transistors with bipolar transistors, which have fundamentally different current handling characteristics. Bipolar transistors can sustain high write currents at scaled dimensions without the reliability degradation that plagues scaled MOS devices, thus reducing area while maintaining or improving reliability
3Speed
If classical in-memory computation is performed using resistive memory arrays, then computation speed is improved, but voltage drops and energy consumption increase with array size
Solution Approach 1:
The patent extracts the active selection function from the resistive memory cells themselves and places it in dedicated bipolar selector transistors. This separation allows the memory cells to be optimized for low-energy storage while the selectors handle the high-current operations, reducing overall energy consumption and voltage drops in large arrays
Solution Approach 2:
The use of bipolar transistors with their high current driving capability provides a buffer against voltage drops before they propagate through the array. The transistors can supply the necessary current headroom to maintain stable operation even in large-scale arrays, cushioning the system against the cumulative effects of resistance and power loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables scalable and reliable in-memory convolutional computation with compact bipolar transistors, allowing for efficient computation of positive and negative weight factors, and overcoming voltage drops and energy consumption issues.
Implementation Method 1
each memory point comprising a phase-change resistive memory cell having a resistive state corresponding to a weight factor
Implementation Method 2
a bipolar selection transistor coupled in series with the cell and having a base terminal coupled with a word line
Implementation Method 3
integrating over the successive time slots the read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells
Data Source
AI summary
In an embodiment a method for convolutional computation (CNVL) of input values with weight factors includes converting the input values to voltage signals and successively applying the voltage signals on selected bit lines in an array of non-volatile memory points over respective time slots, each memory point comprising a phase-change resistive memory cell coupled to a bit line and having a resistive state corresponding to a weight factor, and a bipolar selection transistor coupled in series with the phase-change resistive memory cell and having a base terminal coupled with a word line, wherein the respective voltage signals bias the respective phase-change memory cells, integrating over the successive time slots read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells and flowing through selected word lines and converting the integrated read currents to output values.