Phase Change Memory Die Stacking for Independent Circuit Optimization
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Solution Overview
Problem
Current memory integration approaches that combine memory arrays and control circuits within the same semiconductor die face challenges in independent optimization and performance optimization due to the need for synchronized processing steps, limiting the ability to optimize memory density and device speed separately.
Innovation Solution
The solution involves separating the memory array into a back-end-of-line (BEOL) memory die and the peripheral circuit into a front-end-of-line (FEOL) device die, allowing independent optimization of each component through die-to-die connections using metal-to-metal bonding or through-substrate-via-mediated bonding, enabling independent manufacturing processes for the BEOL memory die and FEOL device die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory array and control circuit are integrated within the same semiconductor die, then device complexity is reduced and manufacturing is simplified, but the ability to independently optimize memory density and device speed is limited
Solution Approach 1:
The patent divides the semiconductor device into two separate dies: a first die containing the memory array and a second die containing the control circuit. This segmentation allows each die to be independently optimized for its specific function - the memory die for high density and the control die for high speed - while eliminating the constraint of synchronized processing steps required by integrated designs.
2Adaptability or versatility
If memory array and control circuit are separated into different dies, then independent optimization of memory density and device speed is enabled, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent combines multiple separate dies (memory die and control die) into a single integrated device package with unified interconnect structures. The interconnect structures span across the different dies to provide electrical connections, effectively merging the functional capabilities of separate components into a cohesive device that maintains independence while achieving integration benefits.
3Manufacturing precision
If synchronized processing steps are used for integrated memory and control circuit, then manufacturing precision is maintained, but productivity and optimization flexibility are reduced
Solution Approach 1:
The patent segments the manufacturing process into independent streams for the memory die and control die. Each die can undergo its own optimized processing sequence without requiring synchronization with the other, allowing parallel production and independent process optimization while maintaining high manufacturing precision through separate process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of a low-cost, high-performance chip assembly structure with optimized memory density and device speed, reducing process variability and improving reliability, particularly with regards to power supply voltage variations.
Implementation Method 1
a switch element comprising a phase change material configured to change between a first resistance state and a second resistance state in response to an applied voltage
Implementation Method 2
a bottom electrode configured to apply a voltage across the phase change material
Data Source
AI summary
A chip assembly structure includes a first chip-containing structure and a second chip-containing structure. The first chip-containing structure includes a back-end-of-line (BEOL) memory die including an array of memory cells and metal interconnect structures. The BEOL memory die is free of any semiconductor material portion having a greater a lateral extent greater than a lateral extent of each memory cell. The first chip-containing structure includes first bonding structures, and a subset of the first bonding structures is electrically connected to the metal interconnect structures in the BEOL memory die. The second chip-containing structure includes a control circuit including field effect transistors which are configured to control operation of the array of memory cells and further includes second bonding structures. The second bonding structures are bonded to the first bonding structures through metal-to-metal bonding or through-substrate-via-mediated bonding.