Phase Change Memory Alignment via Recessed Conductive Lines

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Solution Overview

Problem

Current methods for manufacturing phase change memory devices face challenges in achieving high integration and preventing misalignment between upper conductive lines and switch units, leading to inefficiencies in the manufacturing process.

Innovation Solution

The method involves forming lower conductive lines, memory units, and switch units on a substrate using a combination of damascene and etch techniques, with specific steps including the formation of insulating layers, electrode patterns, and conductive layers, and using etch masks to define parallel lines and recesses, ensuring precise alignment and integration of upper conductive lines and switch units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional manufacturing methods are used for phase change memory devices, then the manufacturing process is simpler, but misalignment between upper conductive lines and switch units occurs and integration is limited

Engineering Contradiction:
Improvealignment precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The method forms recesses in the insulating layer before forming the upper conductive lines, and forms the switch units before forming the upper conductive lines. This preliminary structuring ensures that when the upper conductive lines are formed in the recesses, they automatically align with the underlying switch units, preventing misalignment issues that plague conventional methods.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The manufacturing process is divided into distinct sequential steps: forming lower conductive lines, forming memory units, forming switch units, forming insulating layers with recesses, and finally forming upper conductive lines. This segmentation allows each component to be precisely formed and positioned independently, ensuring proper alignment while maintaining manageable process complexity.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If integration density is increased to achieve higher capacity, then device capacity improves, but misalignment between conductive lines and switch units becomes more critical and harder to control

Engineering Contradiction:
Improveintegration densityVSAvoidalignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The method introduces a vertical dimension by forming recesses in the insulating layer. The upper conductive lines are formed within these recesses, which extend vertically from the insulating layer surface. This vertical structuring provides inherent alignment guidance, allowing higher integration density in the horizontal plane without sacrificing alignment precision, as the recesses act as alignment templates.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If conventional formation methods are used, then manufacturing steps are fewer, but stability and reliability of upper conductive lines and switch units deteriorate

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The method forms an insulating layer with recesses before forming the upper conductive lines. These recesses act as pre-prepared structures that cushion and guide the formation of upper conductive lines, ensuring they are properly positioned and stable. This preliminary preparation prevents misalignment and instability issues, improving device reliability while the systematic approach maintains manufacturing efficiency.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11165022B2Method of manufacturing memory device
Publication Date: 2021.11.02 SAMSUNG ELECTRONICS CO LTD
  • US11165022B2 patent drawing
  • US11165022B2 patent drawing
  • US11165022B2 patent drawing

AI summary

A method of manufacturing a memory device is provided. The method includes the steps of forming a plurality of lower conductive lines on a substrate, forming a plurality of memory units on the plurality of lower conductive lines, forming a switch stack that defines a plurality of first lines, the plurality of first lines extending in parallel in a first direction on the plurality of memory units, forming an upper conductive layer on the switch stack, forming an etch mask that defines a plurality of second lines, the plurality of second lines extending in parallel in a second direction on the upper conductive layer, the second direction being different from the first direction, and forming a plurality of upper conductive lines and a plurality of switch units by etching the upper conductive layer and the switch stack using the etch mask.