Phase Change Memory Bridge Cell With Diode Isolation
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Solution Overview
Problem
Manufacturing high-density memory devices with small active phase change regions and tight process variation specifications is challenging, particularly in achieving reduced reset current requirements for phase change based memory materials in integrated circuits.
Innovation Solution
An array of memory cells is designed with doped semiconductor word lines, pn junctions, and electrode pairs with an insulating member, featuring a phase change bridge across the electrodes, allowing for a small active region and reduced inter-electrode path length, enabling efficient phase change between amorphous and crystalline states with lower current densities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the size of the phase change material element and contact area are reduced to minimize reset current, then the reset current magnitude is reduced, but manufacturing precision and process control become more difficult to meet tight specifications
Solution Approach 1:
The memory cell is segmented into distinct functional regions: a first doped semiconductor region, a second doped semiconductor region forming a pn junction, and a phase change material bridge. This segmentation allows each region to be optimized independently, enabling precise control of the phase change material dimensions while maintaining manufacturability through standardized fabrication processes for the semiconductor regions.
Solution Approach 2:
Different regions of the device have different doping types and material properties optimized for their specific functions. The first doped semiconductor region and second doped semiconductor region create localized electrical fields that confine and control the current density in the phase change material bridge, enabling small active regions with precise current control that meets manufacturing specifications.
2Productivity
If the active phase change region size is reduced to achieve high-density memory, then the memory device density is improved, but the reset current control and phase change reliability become more challenging
Solution Approach 1:
The device utilizes changes in electrical parameters (current density, voltage) controlled by the pn junction to reliably induce phase changes in the small active region. The pn junction structure enables precise control of current density distribution, ensuring that sufficient current is concentrated in the small phase change material bridge to achieve reliable phase transitions despite the reduced size for high density.
3Power
If the inter-electrode path length is reduced to minimize reset current, then the current density efficiency is improved, but the manufacturing process complexity increases to meet tight specifications
Solution Approach 1:
The pn junction structure acts as an intermediary that mediates between the electrodes and the phase change material bridge. It provides a controlled interface that concentrates and directs current flow through the thin insulating member and phase change material, achieving high current density efficiency in a short inter-electrode path while using standard semiconductor fabrication processes to manage manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the production of high-density memory devices with reduced cell sizes and tight process variation specifications, minimizing the reset current needed for phase change, thereby enhancing the performance and scalability of phase change based memory devices.
Implementation Method 1
The memory material has at least two solid phases... The change from the amorphous to the crystalline state... The change from crystalline to amorphous, referred to as reset herein
Implementation Method 2
A plurality of second doped semiconductor regions having a second conductivity type opposite the first conductivity type, second doped semiconductor regions in the plurality of second doped semiconductor regions on corresponding word lines and defining respective pn junctions therebetween
Implementation Method 3
The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data
Implementation Method 4
pairs include respective first and second electrodes and an insulating member between the first and second electrodes
Data Source
AI summary
Memory cells are described along with arrays and methods for manufacturing. An embodiment of a memory cell as described herein includes a second doped semiconductor region on a first doped semiconductor region and defining a pn junction therebetween. A first electrode on the second doped semiconductor region. An insulating member between the first electrode and a second electrode, the insulating member having a thickness between the first and second electrodes. A bridge of memory material across the insulating member, the bridge having a bottom surface and contacting the first and second electrodes on the bottom surface, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.