Variable Resistance Memory Buffering for Flash Write Speed
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Solution Overview
Problem
Conventional NAND flash memory systems face inefficiencies in programming operations due to their erase-before-write characteristic and limited overwrite capabilities, leading to reduced operating speed and increased complexity, cost, and power consumption when used with volatile memory systems.
Innovation Solution
A memory system comprising a NAND flash memory and a resistance variable memory, such as phase change memory, where data is programmed in the most efficient memory type based on page data accumulation, with the controller managing data transfer between the two to optimize programming speed and reduce overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is programmed in NAND flash memory using erase-before-write characteristic, then data can be stored permanently, but programming speed is reduced and operating complexity increases
Solution Approach 1:
The memory system is segmented into two distinct memory types: NAND flash memory for long-term permanent storage and phase change memory for temporary high-speed buffering. This segmentation allows each memory type to operate in its optimal performance regime, with phase change memory handling rapid write operations and NAND flash memory ensuring durable retention, thereby resolving the contradiction between programming speed and data retention.
Solution Approach 2:
Phase change memory serves as an intermediary between the host system and NAND flash memory. It acts as a buffer that receives data from the host, performs rapid programming operations, and then transfers the data to NAND flash memory for permanent storage. This intermediary role eliminates the need for direct erase-before-write operations in NAND flash, significantly improving programming speed while maintaining data retention reliability.
2Reliability
If conventional NAND flash memory is used with volatile memory systems, then data can be stored, but device complexity and power consumption increase
Solution Approach 1:
The memory system achieves multi-functionality by combining NAND flash memory's permanent storage capability with phase change memory's high-speed buffering and overwrite capabilities. The phase change memory layer provides additional functions including temporary storage, write buffering, and enabling rapid data updates without requiring complex erase operations in the NAND flash layer, thereby reducing overall system complexity while enhancing storage reliability.
3Adaptability or versatility
If data is programmed in small pages frequently, then data can be updated, but overhead operations increase and programming efficiency decreases
Solution Approach 1:
The system performs preliminary actions by accumulating multiple small page writes in the phase change memory buffer before transferring to NAND flash memory. This buffering approach allows frequent small updates to be accumulated efficiently in the high-speed phase change memory, then flushed in bulk to NAND flash in larger super-page operations, significantly improving programming efficiency while maintaining flexible data update capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operating speed and reliability of the memory system by skipping unnecessary read operations and improving threshold voltage distribution, while reducing complexity, cost, and power consumption by leveraging the overwrite capabilities of phase change memory.
Implementation Method 1
a resistance variable memory, such as a phase change memory
Data Source
AI summary
A storage device includes a variable resistance memory, a flash memory and a controller. The flash memory includes a plurality of memory cells connected to a plurality of word lines. The controller is configured to receive data from an external device and program the received data in the variable resistance memory or the flash memory according to a quantity of data to be programmed in the flash memory. Further, the controller is configured to read from the variable resistance memory and program the read data in the flash memory, when the quantity of data accumulated in the variable resistance memory corresponds to a super page of data.