Multi-Bit Phase Change Memory Cell Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing phase change memory cells can only store one bit of data, limiting data storage capacity, as they rely on a single resistance state that is either low or high, and lack the ability to independently program and read multiple memory regions.

Innovation Solution

A multiple bit phase change memory cell design with memory regions of varying geometries and resistances, where each region is independently programmable and readable by adjusting reset currents and set voltages, allowing for multiple bits to be stored in a single cell by measuring resistance between electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a single phase change material layer is used, then the memory cell structure is simple, but the data storage capacity is limited to one bit

Engineering Contradiction:
Improvedata storage capacityVSAvoidmemory cell structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The single phase change material layer is segmented into multiple distinct memory regions (first memory region, second memory region, third memory region) with different geometries. Each region can be independently programmed and read, enabling multi-bit storage (2 bits per cell) while maintaining a relatively simple single-layer structure. The regions are separated by conductive barrier layers that allow independent electrical access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different memory regions within the same phase change material layer are given different local geometries (different surface areas, different volumes) to create distinct electrical characteristics. The first memory region has a larger surface area than the second, and the third has a different geometry, allowing each region to have unique reset currents and set voltages for independent control.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If memory regions have the same geometry, then the manufacturing process is simple, but independent programming of multiple regions is not possible

Engineering Contradiction:
Improveindependent programming capabilityVSAvoidgeometry control
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Each memory region is given a distinct local geometry within the phase change material layer. The first memory region has a different surface area than the second, and the third has yet another geometry. These geometric variations create different electrical characteristics (different reset currents and set voltages) that enable independent programming of each region while maintaining a planar single-layer structure that is manufacturable.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If multiple phase change material layers are stacked, then multi-bit storage is achieved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvedata storage capacityVSAvoidmanufacturing process
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

Instead of stacking multiple phase change material layers, the invention segments a single phase change material layer into multiple independently addressable memory regions. This segmentation approach achieves multi-bit storage (2 bits per cell) while avoiding the manufacturing complexity of stacking, as it uses a planar single-layer structure with conductive barrier layers for regional isolation and access.

Inventive Principle:
Principle #1Segmentation

4Measurement precision

If all memory regions have the same resistance, then the structure is uniform and simple, but resistance measurement cannot unambiguously determine the state of multiple regions

Engineering Contradiction:
Improvestate determination accuracyVSAvoidmemory region properties
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Different memory regions are given different local geometries (different surface areas, volumes) which result in different electrical resistances. The first memory region has a different resistance than the second, and the third has yet another resistance. This resistance differentiation allows the read operation to unambiguously determine the state of each region by measuring the total resistance and comparing it against known resistance values for each region's crystalline and amorphous states.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables increased data storage by allowing a single resistance measurement to unambiguously determine the state of multiple memory regions, facilitating independent programming and reading of each bit, thereby enhancing storage capacity and flexibility.

Implementation Method 1

Applying a suitable current in the low resistance crystalline state causes sufficient heating to change the state to the high resistance amorphous state

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

phase change material that changes state, generally between a low and a high resistance state

Methodology Applied
Scientific EffectPhase change: Phase Change

Data Source

PatentEP2272113B1Multiple bit phase change memory cell
Publication Date: 2015.11.25 NXP BV
  • EP2272113B1 patent drawingFigure 1~2

AI summary

A phase change memory cell has more than one memory region (14,18) each being a narrowed region of phase change memory material (2) extending between first and second electrodes (4,6). Each of the plurality of memory regions (14, 18) can be programmed to be in a low resistance state or a high resistance state by applying suitable programming conditions of current and/or voltage. The resistances of the high resistance states and the programming conditions to convert the high resistance states to the low resistance state are different in each of the plurality of memory regions.