Sub-lithographic Phase Change Memory Cell via Tapered Contact
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Solution Overview
Problem
Existing phase change memory devices face limitations in reducing the magnitude of the reset current required for transitioning from a crystalline to an amorphous state, which is constrained by the minimum feature size of manufacturing equipment, leading to non-uniformity and unreliability in high-density memory devices.
Innovation Solution
A method for forming memory cells with small active regions using a multi-step process involving the deposition of conductor and dielectric layers, etching, and void creation to achieve precise control over the contact area and size of the phase change material, allowing for sublithographic dimensions and reliable manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the size of the phase change material element is reduced to minimize reset current magnitude, then the reset current can be reduced, but the manufacturing precision and uniformity deteriorate due to sub-lithographic dimensions
Solution Approach 1:
The patent transitions from planar 2D lithographic patterning to 3D vertical structuring by forming tapered contact holes through multiple etching steps. The contact area is defined by the hole geometry rather than lithographic features, enabling sub-lithographic dimensions while maintaining manufacturing precision through controllable etch profiles and selective removal of sacrificial layers.
Solution Approach 2:
The patent divides the contact formation process into multiple discrete steps: forming initial contact holes, depositing sacrificial layers, performing selective etching to create tapered profiles, and removing sacrificial material. This segmentation allows precise control over the final contact geometry and size, achieving uniform sub-lithographic dimensions that would be impossible with single-step lithography.
2Use of energy by moving object
If the contact area between electrodes and phase change material is reduced to achieve higher current densities, then the reset current magnitude is reduced, but the device complexity increases
Solution Approach 1:
The patent introduces sacrificial dielectric layers as intermediary materials that temporarily occupy space during fabrication and are selectively removed to define the final contact geometry. These sacrificial layers act as placeholders that simplify the overall process by enabling precise contact area definition through selective etching rather than direct lithographic patterning at sub-lithographic scales.
Solution Approach 2:
The patent controls contact area by changing geometric parameters of the contact holes, specifically creating tapered profiles with controlled angles and depths. By adjusting etch parameters, hole depth, and sacrificial layer thickness, the final contact area is precisely controlled without increasing lithographic complexity, achieving higher current densities through geometry optimization.
3Ease of manufacture
If standard integrated circuit manufacturing processes are used, then the manufacturing ease is maintained, but the minimum feature size limits the density of memory cells
Solution Approach 1:
The patent embeds multiple fabrication steps within a unified process flow that uses standard semiconductor manufacturing equipment. The complex 3D contact structures are built by nesting deposition, etching, and removal steps within each other, creating sophisticated geometries using conventional tools and processes rather than requiring new lithographic capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of reset current magnitude and improves the uniformity and reliability of phase change memory devices, facilitating the development of high-density memory devices with smaller feature sizes.
Implementation Method 1
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase.
Implementation Method 2
Current heats the material and causes transitions between the states.
Implementation Method 3
The generally amorphous state is characterized by higher resistivity than the generally crystalline state; this difference in resistance can be readily sensed to indicate data.
Data Source
AI summary
A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory material element in contact with the first electrode. A second electrode is created to contact the memory material element.