Dynamic Pulse Control for Phase Change Memory Degradation
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Solution Overview
Problem
Phase change memory cells degrade over time due to current flow, leading to decreased resistance in both amorphous and crystalline states, causing operational issues and errors in memory arrays, especially when widespread failures occur, which are costly to address through traditional memory verify algorithms.
Innovation Solution
A memory device with a control circuit that adjusts the reset and set operations based on indicators of degraded memory state retention, such as the number of lifetime cycles, by varying parameters like energy application period, current, and total energy, to mitigate degradation and prevent errors in phase change memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory verify algorithms are used to address widespread failures, then memory errors can be corrected, but time cost and throughput are significantly reduced
Solution Approach 1:
The control circuit proactively adjusts operation parameters based on the number of lifetime cycles before failures actually occur. By predicting degradation trends and preemptively modifying reset and set operations, the system prevents widespread failures rather than reacting to them, thereby avoiding time-consuming verify algorithms.
Solution Approach 2:
The system continuously monitors memory cell degradation through the lifetime cycle counter and uses this feedback to dynamically adjust operation parameters. This closed-loop control enables real-time adaptation to degradation, maintaining reliability without requiring periodic full-array verify operations that consume significant time.
2Reliability
If operation parameters are adjusted frequently to mitigate degradation, then memory retention is improved, but device complexity and control overhead increase
Solution Approach 1:
The control circuit adjusts specific operation parameters (pulse width, amplitude, or number of pulses) for reset and set operations based on lifetime cycle count. This targeted parameter modification approach improves retention while keeping the control mechanism relatively simple, as it only requires monitoring cycle count and applying predetermined parameter adjustments rather than complex real-time optimization.
Solution Approach 2:
The system transitions from static operation parameters to dynamic parameters that change with the number of lifetime cycles. The control circuit automatically adapts reset and set operation characteristics as the memory ages, enabling continuous optimization of retention without requiring complex external control mechanisms.
3Strength
If the volume of phase change material undergoing state change is reduced, then stress on the material is limited, but degradation from current flow still occurs
Solution Approach 1:
The control circuit modifies operation parameters (such as pulse width, amplitude, or number of pulses) for reset and set operations based on the number of lifetime cycles. This compensates for the reduced volume of phase change material by adjusting the energy delivery to maintain sufficient state transitions, thereby preserving reliability despite limited material volume.
Solution Approach 2:
The system applies compensatory energy delivery in advance to account for the limited volume of phase change material. By adjusting operation parameters proactively based on lifetime cycle count, the system ensures that sufficient energy is delivered to achieve reliable state changes despite the constrained material volume that is more susceptible to degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses degraded memory retention and reduces errors in sense amplifier operations by dynamically adjusting operations based on cycle counts and resistance changes, improving the longevity and reliability of phase change memory arrays.
Implementation Method 1
Phase change memory cells degrade with continued regular operation. It is believed that the degradation is caused by the flow of current through the phase change memory cell.
Implementation Method 2
The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. In several embodiments, the reset operation changes at least one phase change memory cell in the array to the amorphous phase, and the set operation changes at least one phase change memory cell in the array to the crystalline phase.
Data Source
AI summary
The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array.