Hierarchical Bit Line Structure for Phase Change Memory Uniformity
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Solution Overview
Problem
Phase change memory devices face issues with non-uniform resistance between memory cells and reading/writing circuits due to differences in physical distance, leading to errors in programming operations as the write current varies, affecting data storage accuracy.
Innovation Solution
The implementation of a phase change memory device with a hierarchical bit line structure featuring global and local bit lines at multiple wiring levels, where column selection transistors couple local bit lines to global bit lines at different levels, reducing resistance and ensuring uniform write and read currents across all memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a hierarchical bit line structure with global and local bit lines is used to provide high capacity and high integration, then storage capacity and integration density are improved, but resistance varies according to the position of the selected phase change memory cell with respect to the writing circuit or reading circuit
Solution Approach 1:
The bit line structure is segmented into global bit lines and local bit lines, where global bit lines extend over multiple local bit lines and local bit lines are coupled to individual memory cells. This segmentation allows the global bit lines to be positioned at multiple wiring levels to distribute and reduce resistance across different regions of the memory array, ensuring more uniform current distribution to cells at various distances from the writing/reading circuit.
Solution Approach 2:
The global bit lines are positioned at two or more different wiring line levels over the semiconductor substrate, adding a vertical dimension to the bit line structure. This three-dimensional arrangement allows global bit lines to overlap with and connect to multiple local bit lines at different levels, reducing the physical distance and resistance between the writing/reading circuit and memory cells located at different positions in the array.
2Area of stationary object
If local bit lines are extended over the semiconductor substrate to couple distant memory cells, then coverage and accessibility are improved, but resistance from the writing circuit to distant memory cells increases
Solution Approach 1:
Global bit lines serve as intermediary conductors between the writing/reading circuit and local bit lines that connect to individual memory cells. The global bit lines are positioned at multiple wiring levels to provide intermediate connection points, reducing the direct distance and resistance between the writing circuit and distant memory cells through these intermediary global bit line connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures uniform write and read currents, reducing the likelihood of errors in programming operations and enhancing data storage accuracy by minimizing the impact of physical distance on resistance, thereby improving the overall performance of phase change memory devices.
Implementation Method 1
data is written using Joule heat. This Joule heat is generated when a write current is supplied to the phase change material having a predetermined resistance
Implementation Method 2
the phase change material transforms into the amorphous state. Alternatively, the phase change material is heated to temperature that is higher than a crystallization temperature but less than the melting temperature, kept at the temperature for a predetermined time, and then cooled. By this process, the phase change material transforms into the crystalline state
Data Source
AI summary
A phase change memory device includes a semiconductor substrate which includes a plurality of phase change memory cells, a plurality of local bit lines extending over the semiconductor substrate, each of the plurality of local bit lines being coupled to the plurality of phase change memory cells, and a plurality of global bit lines extending over the plurality of local bit lines, each of the plurality of global bit lines being selectively coupled to the plurality of local bit lines. The plurality of global bit lines are located at two or more different wiring line levels over the semiconductor substrate.