Phase Changeable Memory Cell Array With Thermal Isolation Regions
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Solution Overview
Problem
Phase changeable memory devices face issues with thermal disturbances and reduced programming capacity due to etching processes, leading to degradation and unreliable data storage, especially as integration density increases.
Innovation Solution
A phase changeable memory cell array design featuring a phase changeable material pattern with regions of varying thermal conductivity, where amorphous impurity-implanted regions act as isolation layers to prevent thermal disturbances and reduce etching damage, allowing for higher integration density without compromising data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a phase changeable material layer is shaped as an island using an etching process, then the phase changeable material can be disposed in each memory cell, but the properties of the separated surface change and the composition deteriorates over time
Solution Approach 1:
An interlayer dielectric layer is introduced as an intermediary between the phase changeable material layer and the external environment. This mediator prevents direct exposure of the phase changeable material to etching processes and environmental degradation, thereby maintaining composition stability and data storage reliability while still allowing the material to be shaped into islands for memory cell formation.
2Productivity
If integration density is increased, then more memory cells can be packed, but thermal disturbances between adjacent cells increase
Solution Approach 1:
The phase changeable material layer is segmented into discrete island shapes, with each island corresponding to a memory cell. This segmentation creates physical and thermal isolation between adjacent memory cells, preventing thermal disturbances from propagating between cells even as integration density increases. The island configuration allows tighter packing while maintaining thermal boundaries.
3Ease of manufacture
If the phase changeable material layer is exposed to etching processes, then the material can be patterned, but the amount of normal phase changeable region available for programming is reduced
Solution Approach 1:
The etching process is applied locally and selectively to specific regions where patterning is required, rather than uniformly across the entire phase changeable material layer. This localized approach allows precise formation of island structures in memory cell regions while preserving the integrity and quantity of phase changeable material in non-etched areas, maintaining sufficient programming capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents thermal disturbances between adjacent memory cells and maintains data storage reliability by using amorphous impurity-implanted regions with lower thermal conductivity, enabling more efficient and durable phase changeable memory cell arrays.
Implementation Method 1
amorphous impurity-implanted regions with lower thermal conductivity than the plurality of first regions
Implementation Method 2
when a write current flows through the switching device and the lower electrode, heat is generated at an interfacial surface between the phase changeable material pattern and the lower electrode
Implementation Method 3
The generated heat changes the phase changeable material pattern into an amorphous or crystalline state
Data Source
AI summary
A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.