Phase Change Memory Read Margin via Iterative Current Control
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Solution Overview
Problem
Phase change memory devices face challenges in reliably distinguishing between crystalline and amorphous states due to close resistance distributions, leading to degraded reliability and increased read errors, especially with temperature variations affecting the reset resistance more significantly than the set resistance.
Innovation Solution
A method and device that iteratively apply a level-controlled write current to phase change memory cells until their resistive state falls within defined resistance distributions, using reference cells to adjust the write current and maintain a stable read margin, and incorporating temperature compensation to account for resistance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase change memory devices use conventional resistance-based state distinction, then the memory device can store data using phase change materials, but the close resistance distributions between crystalline and amorphous states lead to degraded reliability and increased read errors
Solution Approach 1:
The patent changes the measurement parameter from simple resistance to a composite parameter combining resistance and its temperature coefficient. This allows differentiation between states that have similar resistance values but different temperature dependencies, thereby improving state distinction precision and read reliability
Solution Approach 2:
The patent effectively creates a composite measurement approach by combining two measurement aspects (resistance magnitude and temperature coefficient) into a unified state detection method. This composite approach enables reliable state distinction even when individual resistance values are close
2Reliability
If temperature compensation is not implemented, then the device operation is simpler, but resistance variations due to temperature changes affect the reset resistance more significantly than the set resistance, leading to read errors
Solution Approach 1:
The patent implements feedback by measuring the temperature coefficient of resistance and using this information to compensate for temperature-induced resistance variations. The system continuously monitors temperature effects and adjusts the state determination accordingly, improving read accuracy without requiring complex external temperature control
Solution Approach 2:
The phase change memory cell itself provides the temperature coefficient information needed for compensation. By measuring the resistance change with temperature, the device self-characterizes its temperature sensitivity and uses this information to correct for temperature effects during normal operation
3Reliability
If iterative level-controlled write current is not applied, then the programming process is faster, but the resistive state may not fall within defined resistance distributions, degrading read margin
Solution Approach 1:
The patent applies preliminary actions by using reference cells to pre-determine appropriate write current levels before programming the actual memory cells. This preliminary characterization allows subsequent programming to use optimized current levels that reliably achieve the desired resistance distributions without requiring excessive iteration
Solution Approach 2:
The patent implements dynamic adjustment of write current levels based on the current state of the memory cell. The iterative process adapts the programming current in real-time, increasing or decreasing it as needed to guide the resistance value toward the target distribution, thereby achieving good read margins efficiently
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the read margin and reliability of phase change memory devices by ensuring accurate state distinction and reducing read errors across varying temperatures, enabling effective storage of both 1-bit and multi-bit data.
Implementation Method 1
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases
Implementation Method 2
The phase change material in a phase change memory device is typically converted to the amorphous state by heating the material to above a predetermined melting temperature
Implementation Method 3
The phase change material in a phase change memory device is typically converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material
Data Source
AI summary
A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.