Phase Change Memory Device Shared Electrode Integration
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Solution Overview
Problem
Conventional phase change memory devices require large gate widths for MOS transistors to supply sufficient current for data rewriting, leading to increased chip area and obstacles to high integration due to the need for larger unit cell areas.
Innovation Solution
A phase change memory device configuration where multiple phase change memory elements share a single MOS transistor, with a lower electrode structure and multi-layer electrode structures to reduce layout area per bit, enabling efficient current supply and high integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width of the MOS transistor is increased to supply sufficient current for data rewriting, then the current supply capability is improved, but the chip area increases
Solution Approach 1:
The invention segments the relationship between MOS transistors and phase change memory elements by connecting one MOS transistor to multiple phase change memory elements through a shared lower electrode structure. This segmentation allows the MOS transistor gate width to be reduced while still providing sufficient current to multiple memory elements via the common electrode, thereby reducing chip area while maintaining current supply capability.
Solution Approach 2:
The lower electrode structure serves as a universal connection point that multiple phase change memory elements share with a single MOS transistor. This multi-functional electrode enables one MOS transistor to control and supply current to multiple memory elements simultaneously, improving area efficiency while maintaining the required current supply capability for data rewriting.
2Power
If the gate width of the MOS transistor is increased to supply sufficient current for data rewriting, then the rewriting capability is improved, but the unit cell area increases
Solution Approach 1:
The invention segments the unit cell structure by sharing the MOS transistor and lower electrode among multiple phase change memory elements. This segmentation reduces the area occupied by each unit cell while maintaining the rewriting capability, as the shared MOS transistor can still supply sufficient current through the common lower electrode to multiple memory elements for data rewriting operations.
Solution Approach 2:
The invention merges multiple phase change memory elements with a single MOS transistor through a shared lower electrode structure. This merging reduces the overall unit cell area by eliminating redundant MOS transistors and lower electrodes, while the combined structure maintains the capability to supply sufficient current for data rewriting across all connected memory elements.
3Power
If the chip area is increased to accommodate larger unit cells, then the MOS transistor can supply sufficient current, but the integration density decreases
Solution Approach 1:
The invention segments the current supply path by introducing a shared lower electrode that distributes current from one MOS transistor to multiple phase change memory elements. This segmentation allows the MOS transistor to maintain sufficient current supply capability while occupying less area, thereby increasing integration density without sacrificing rewriting capability.
Solution Approach 2:
The shared lower electrode structure provides universal current distribution to multiple memory elements from a single MOS transistor. This multi-functional design enables one MOS transistor to serve multiple memory elements, increasing the number of memory elements per chip area and thereby improving integration density while maintaining adequate current supply for data rewriting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the layout area per bit, allowing for high integration of phase change memory devices by sharing a MOS transistor among multiple phase change memory elements, effectively addressing the challenge of increasing storage capacity while maintaining compactness.
Implementation Method 1
the phase change memory element may change between low-resistance crystalline state and high-resistance amorphous state by heat generated when supplying current to corresponding said second plug and is capable of rewriting data
Implementation Method 2
heat generated when supplying current to corresponding said second plug
Data Source
AI summary
A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.