Phase Change Memory Cell With Side Wall Heater
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Solution Overview
Problem
Conventional phase change memory (PRAM) and resistance change memory (RRAM) devices face challenges in miniaturization due to high reset and read currents, which limit memory cell size and integration, primarily because of the large cross-section of the GST film and heater element, leading to increased current requirements and heat conduction issues.
Innovation Solution
The solution involves forming a phase change material, such as chalcogenide glass, into a thin film on the gate of a cell transistor with heater resistance elements on both sides, allowing for a significant reduction in the cross-section of the GST film and heater element, enabling lower current operation and heat confinement, thereby minimizing the write, reset, and read currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the cross-section of the GST film and heater element is reduced to decrease current, then the write current and read current decrease, but the heat density increases causing thermal interference
Solution Approach 1:
The patent transitions from planar heater elements to three-dimensional side wall heater structures. The heater is formed on the side wall of the gate electrode, extending vertically along the gate height, which increases the heater surface area without increasing the planar footprint. This dimensional change allows heat to be distributed over a larger volume of the GST film, reducing heat density while maintaining effective heating for phase change.
Solution Approach 2:
The patent applies localized heating by forming heater elements specifically on the side walls of the gate electrode, directly adjacent to the GST film region that requires phase change. This localized approach concentrates heating where needed while minimizing thermal interference with adjacent memory cells, achieving effective phase change with reduced overall heat density.
2Area of stationary object
If the memory cell size is reduced for high integration, then the number of memory cells per area increases, but the write current and read current increase due to smaller cross-section
Solution Approach 1:
The side wall heater configuration exploits the vertical dimension (gate height) to increase heater surface area. This allows the heater to maintain sufficient heating capability even when the planar dimensions of the memory cell are reduced, enabling high integration without proportionally increasing current requirements.
Solution Approach 2:
The heater element is nested on the side wall of the gate electrode structure, utilizing the existing vertical space of the transistor gate. This nesting approach allows the heater to be integrated within the memory cell structure without adding significant planar area, enabling miniaturization while maintaining heating efficiency.
3Volume of moving object
If the GST film cross-section is reduced to miniaturize the device, then the device size decreases, but the reset current increases due to higher resistance
Solution Approach 1:
The side wall heater configuration compensates for the reduced GST film cross-section by increasing the heater surface area in the vertical dimension. This allows sufficient heat energy to be delivered to the smaller GST volume, maintaining effective phase change capability despite the reduced cross-section and associated higher resistance.
Solution Approach 2:
The patent changes the geometric parameters of the heater element, specifically increasing its surface area through the side wall configuration. This parameter change compensates for the increased resistance of the miniaturized GST film, maintaining the energy balance required for phase change operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a substantial decrease in write, reset, and read currents, enabling the realization of a 4F2 memory cell size, improved heat density, and reduced cell size, while maintaining high-speed and low-power operation with reduced heat interference and resistance variation.
Implementation Method 1
both ends of which are connected to a source and a drain of the cell transistor... resistance wirings becomes a heater
Data Source
AI summary
According to one embodiment, a phase change memory includes a memory cell, a select transistor, and a memory cell array. The memory cell includes a chalcogenide wiring, resistance wirings and a cell transistor. The chalcogenide wiring becomes a heater. One end of a plurality of memory cells with sources and drains connected in series is connected to a source of the select transistor. The bit line is connected a drain of the select transistor. The memory cell array is obtained by forming a memory cell string.