Phase Change Memory Word Line Floating Sequence
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Solution Overview
Problem
Resistive memory devices face challenges in increasing the sensing margin and the number of reading cycles due to read disturb characteristics, where a selected memory cell is incorrectly recognized as being in a reset state after repeated read operations.
Innovation Solution
The memory device employs a method where the selected word line and an adjacent word line are floated at different times during the read operation, reducing the capacitance value between them and thereby increasing the read disturb margin, allowing for more reading cycles without reducing the sensing margin of memory cells with low threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same word line is floated throughout the entire read operation, then the read operation is simple, but the sensing margin decreases and reading cycles are limited
Solution Approach 1:
The patent applies dynamics by making the floating state of word lines time-dependent. The selected word line is floated during the sensing period, while adjacent word lines are floated at different times. This dynamic approach allows the system to optimize sensing margin during critical read operations while managing capacitance effects, thereby increasing reliability without requiring complete operational redesign.
Solution Approach 2:
The patent segments the floating operation into distinct phases: the selected word line is floated during sensing, while adjacent word lines are floated at different time intervals. This segmentation allows independent optimization of sensing performance and capacitance management, resolving the contradiction between sensing margin and operational simplicity.
2Reliability
If adjacent word lines are floated simultaneously with the selected word line, then the operation is simplified, but the read disturb margin decreases
Solution Approach 1:
The patent applies preliminary action by floating the selected word line before floating adjacent word lines. The selected word line is floated during the sensing period when read disturb is most critical, while adjacent word lines are floated subsequently. This timing sequence pre-establishes the optimal capacitance state for sensing while still managing read disturb effects.
Solution Approach 2:
The patent makes the floating operation dynamic by using different time intervals for selecting and floating word lines. The selected word line is floated during sensing, while adjacent word lines are floated at different times. This dynamic timing control increases read disturb margin without requiring complex simultaneous control mechanisms.
3Reliability
If the capacitance value between word lines is reduced, then the read disturb margin increases, but the implementation becomes more complex
Solution Approach 1:
The patent changes the temporal parameter of word line floating rather than physically altering capacitance values. By controlling when word lines are floated (selected word line during sensing, adjacent word lines at different times), the system effectively reduces read disturb margin without requiring complex physical modifications to reduce capacitance between word lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the read disturb margin of memory cells with high threshold voltages, increasing the number of reading cycles while maintaining accurate data determination for memory cells with low threshold voltages.
Implementation Method 1
a resistive memory device may write or erase data by changing a resistance of its memory cells... having a phase change material
Data Source
AI summary
A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.