Hierarchical Row Decoder for Phase-Change Memory Power Optimization

The row decoder is segmented into multiple independent decoding stages (first row decoder and second row decoder), each handling a subset of wordlines. This segmentation allows selective activation of only the decoding stage corresponding to the desired wordline range, thereby reducing the number of simultaneously active selector transistors and lowering static power consumption during reading operations.

The patent implements dynamic control of decoder activation through enable signals (e.g., first enable signal and second enable signal) that selectively activate only the required decoding stage based on the address input. This dynamic switching ensures that only necessary selector transistors remain in active state during reading, minimizing static power dissipation while maintaining full access capability.

The row decoder area is divided into separate decoding stages (first row decoder and second row decoder), each with its own selector transistors and control logic. By segmenting the decoder, the active area for any single decoding operation is reduced since only one stage needs to be fully active at a time, while the total area accommodates multiple stages in a distributed manner throughout the memory array.

The patent employs a hierarchical decoder structure where first row decoders and second row decoders are distributed across different memory array regions. Each decoder stage is nested within its corresponding memory block, allowing the overall decoder area to be distributed and shared across multiple memory sections rather than concentrated in a single large block.

The patent implements dynamic voltage switching capability where the same wordline infrastructure can operate at different voltage levels depending on the operation mode. During programming, high voltage is applied to achieve phase-change material switching, while during reading, low voltage is used to detect resistance states without causing unintended phase changes. This dynamic voltage adaptation is enabled by controlled activation of selector transistors and appropriate biasing schemes.

The electrical parameters (voltage and current) of the wordlines are dynamically changed based on the operation type. The patent employs different voltage levels and current magnitudes for programming versus reading operations, with the row decoder controlling these parameter changes through selective transistor activation and enable signals. This parameter adaptation allows the system to meet the distinct electrical requirements of each operation mode using the same hardware infrastructure.