Phase-Shifted Clock Circuit With Capacitor Delay Control

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Solution Overview

Problem

Conventional phase shifted clock generators for integrated circuits require complex and large-size circuitries, leading to high power consumption, making them unsuitable for low-power applications such as wearable devices.

Innovation Solution

A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit, where the phase difference between the phase shifted clock signal and the reference clock signal is controlled by adjusting the delay of the delay circuit based on a control voltage, using a switch to manage the charging and discharging of the capacitor, thereby reducing the complexity and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional phase shifted clock generators are used, then the clock signal phase shifting function is achieved, but the circuit complexity and power consumption increase

Engineering Contradiction:
Improvecircuit complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The phase shifted clock generator is divided into three main functional modules: a delay circuit that receives the reference clock signal and generates the phase shifted clock signal, a control circuit that generates control voltages based on clock signals, and a capacitor that stores the control voltage to adjust the delay. This segmentation allows each module to perform a specific function with minimal complexity, avoiding the need for large-size circuitries while achieving the required phase shifting capability.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If complex circuitries are used to achieve accurate phase shifting, then the phase accuracy is improved, but the power consumption increases

Engineering Contradiction:
Improvephase accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The invention controls the delay of the delay circuit by adjusting the control voltage stored in the capacitor. By changing the voltage parameter applied to the delay circuit, the phase shift amount can be precisely controlled without requiring complex circuit structures. The control circuit generates appropriate control voltages based on the reference clock signal and phase shifted clock signal, enabling accurate phase shifting through simple voltage adjustment rather than complex circuitry.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution reduces the complexity and power consumption of the phase shifted clock generator, enabling its use in low-power applications like wearable devices without the need for complex circuitries.

Implementation Method 1

a first capacitor. The control circuit may be configured to control, based on the first phase shifted clock signal and the reference clock signal, a first control voltage generated at the first capacitor by at least one of a group consisting of charging and discharging the first capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12164326B2Phase shifted clock generator
Publication Date: 2024.12.10 NXP BV
  • US12164326B2 patent drawing
  • US12164326B2 patent drawing
  • US12164326B2 patent drawing

AI summary

A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.