Phase-Shifted Clock Counter for Precise FPGA Time Measurement
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Solution Overview
Problem
Developing counters in digital integrated circuit technologies with sufficient bit lengths to achieve desired accuracy and precision at high clock frequencies is challenging, and there is a lack of methodologies to verify the integrity of signal traces and connections in semiconductor devices and assemblies, leading to system failures due to cabling and connector issues.
Innovation Solution
A high-speed counter and measurement system using phase-shifted clock signals and Field Programmable Gate Arrays (FPGAs) to measure response times and verify signal trace integrity by generating phase-shifted clocks, incrementing counters, and combining values to generate precise time measurements, which can identify faults and verify connection integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional counters are used at high clock frequencies, then counting speed is improved, but measurement precision deteriorates due to insufficient bit lengths
Solution Approach 1:
The patent divides a single high-frequency clock signal into multiple lower-frequency phase-shifted clock signals. Each phase-shifted clock operates at a reduced frequency, allowing counters to use sufficient bit lengths for accurate counting. The phase shifts ensure that the combined counting results from multiple counters achieve the equivalent time measurement resolution of the original high-frequency clock, thus resolving the contradiction between speed and precision.
2Measurement precision
If phase-shifted clocks are used to improve measurement precision, then counting accuracy is improved, but device complexity increases due to multiple clocks and counters
Solution Approach 1:
The patent employs a single phase-shifting circuit that generates multiple phase-shifted clock signals from one reference clock. This multi-functional approach allows the same hardware infrastructure to serve multiple counting functions simultaneously. The systematic phase-shifting mechanism and uniform counter design reduce overall system complexity compared to using entirely separate timing circuits for each measurement function.
Solution Approach 2:
The patent combines the outputs of multiple counters through addition to produce a final time measurement result. This merging operation integrates the counting results from all phase-shifted clocks, achieving high-precision measurement equivalent to the original high-frequency clock while using lower-frequency individual counters. The combination logic consolidates multiple measurement paths into a single unified result.
3Reliability
If verification capability is added to identify faulty assemblies, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements self-verification capability within the timing system by comparing measured time intervals against expected values. The system automatically identifies anomalies in signal traces and connections without requiring external verification equipment. This built-in self-testing function improves assembly reliability while avoiding additional manufacturing costs for separate verification systems.
Solution Approach 2:
The verification functionality is designed to be integrated into the existing timing measurement system before final assembly completion. By incorporating verification capabilities during the manufacturing process rather than as a post-manufacturing add-on, the system can identify faulty assemblies early, preventing defective products from reaching customers and reducing overall manufacturing costs through early defect detection.
Data Source
AI summary
Methods and apparatus for generating phase-shifted clock signals from a reference clock, connecting the phase-shifted clock signals to a counter module so that the phase-shifted clock signals change values in counters in the counter module, and combining the values in the counters to generate an output signal corresponding to an amount of time. One or more events can be detected at a time corresponding to the output signal. In embodiments, pulses can be transmitted and received at a measure time to evaluate connected devices.