Phase-Shifted Clock Circuit With Constant-Current Delay Control
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Solution Overview
Problem
Conventional phase shifted clock generators for integrated circuits require complex and large-size circuitries, leading to high power consumption, making them unsuitable for low-power applications such as wearable devices.
Innovation Solution
A phase shifted clock generator comprising a delay circuit, a capacitor, and a control circuit that controls a control voltage to adjust the phase difference between the phase shifted clock signal and the reference clock signal, utilizing a switch to manage the control voltage and reduce power consumption by eliminating the need for complex circuitries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase shifted clock generators are used to generate accurate phase shifted clock signals, then phase accuracy is improved, but circuit complexity and size increase, leading to high power consumption
Solution Approach 1:
The patent extracts and eliminates complex circuit components from conventional phase shifted clock generators. By using a simple delay circuit with controllable delay element instead of complex phase-locked loops or multiple buffer stages, the invention removes unnecessary complexity while maintaining phase shifting functionality through the control voltage that adjusts delay based on duty cycle variations
Solution Approach 2:
The patent changes the parameter being controlled from complex circuit configurations to a simple controllable delay parameter. By varying the delay amount through control voltage in response to duty cycle changes, the system achieves accurate phase shifting through parameter adjustment rather than complex structural design
2Adaptability or versatility
If conventional phase shifted clock generators with complex circuitries are used, then phase shifting functionality is achieved, but power consumption increases, making them unsuitable for low-power applications
Solution Approach 1:
The patent removes power-hungry complex circuitry from the phase shifted clock generator design. By extracting only the essential delay function and implementing it with a simple controllable delay circuit responsive to duty cycle variations, the invention achieves phase shifting with minimal power consumption suitable for wearable devices
Solution Approach 2:
The patent implements a self-adjusting mechanism where the delay circuit automatically responds to duty cycle variations through control voltage without requiring additional active control logic. This self-service approach eliminates the need for extra control circuits that would consume additional power
3Reliability
If complex circuitries are used in phase shifted clock generators, then reliable phase shifting is achieved, but device size increases, reducing suitability for compact wearable devices
Solution Approach 1:
The patent extracts and eliminates bulky circuit components from conventional designs. By implementing phase shifting through a compact delay circuit that leverages existing duty cycle variations rather than adding complex phase detection and adjustment circuitry, the invention achieves reliable phase shifting in a minimal area suitable for wearable devices
Data Source
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AI summary
A phase shifted clock generator (104) that includes a delay circuit (202), a capacitor (208), and a control circuit (206) is provided. The delay circuit receives a reference clock signal (RCK) and generates a phase shifted clock signal (OCK). A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage (V1) generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor (208) with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.