Two-Stage Phase Clock Correction for Duty-Cycle Alignment
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Solution Overview
Problem
Memory devices face challenges in distributing high frequency clock signals due to filter-like traces, leading to phase errors and signal degradation, which affect the accuracy of clock signals used for timing operations.
Innovation Solution
A two-stage duty-cycle adjustment process is implemented to correct phase errors in low frequency clock signals generated from a high frequency clock signal, ensuring proper spacing and alignment of clock signals, thereby maintaining timing information integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high frequency clock signals are distributed through traces, then timing information can be conveyed, but phase errors and signal degradation occur due to filter-like trace characteristics
Solution Approach 1:
The patent introduces an intermediary correction mechanism that processes clock signals through multiple stages. A first correction circuit adjusts phase errors in a first clock signal, and a second correction circuit adjusts phase errors in a second clock signal derived from the first. This intermediary correction process compensates for the phase degradation that occurs during high-frequency signal distribution through traces.
Solution Approach 2:
The patent implements feedback-based phase correction by monitoring the phase relationships between clock signals and applying corrective adjustments. The correction circuits receive feedback about phase errors and dynamically adjust the clock signals to maintain accurate timing relationships, counteracting the phase degradation caused by trace filtering effects.
2Adaptability or versatility
If multiple clock signals are generated to convey timing information, then operational flexibility is improved, but component imperfections cause non-ideal phase offsets between signals
Solution Approach 1:
The patent uses feedback mechanisms to detect and correct phase offsets between multiple clock signals. The correction circuits continuously monitor the phase relationships and apply adjustments to maintain ideal phase offsets, compensating for manufacturing imperfections in the clock signal generation components.
Solution Approach 2:
The patent introduces correction circuits as intermediary elements between the clock signal generation stage and the usage stage. These intermediaries actively manage and correct phase relationships, ensuring that multiple clock signals maintain accurate phase offsets despite component variations and manufacturing tolerances.
Data Source
AI summary
Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.