Two-Stage Phase Clock Correction for Even Duty-Cycle Spacing
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Solution Overview
Problem
Memory devices face challenges in distributing high frequency clock signals due to filter-like traces, leading to phase errors and signal degradation, which affect the accuracy of clock signals used for timing operations.
Innovation Solution
A two-stage duty-cycle adjustment process is implemented to correct phase errors in low frequency clock signals, ensuring they are evenly spaced, allowing them to accurately represent the timing information of high frequency clock signals and maintain signal integrity throughout the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high frequency clock signals are distributed through traces, then timing information can be conveyed across the device, but phase errors and signal degradation occur due to filter-like trace characteristics
Solution Approach 1:
The patent divides the clock signal distribution into multiple frequency domains by generating both high frequency clock signals for speed-critical paths and low frequency clock signals for phase-accurate timing reference. This segmentation allows different parts of the device to use appropriate clock frequencies for their specific functions, resolving the contradiction between speed and phase accuracy.
Solution Approach 2:
The patent introduces low frequency clock signals as an intermediary reference that preserves accurate timing information. These low frequency signals act as a mediator between the high frequency clock signals and the timing-critical operations, allowing phase errors in high frequency distribution to be corrected by reference to the more stable low frequency reference.
2Adaptability or versatility
If multiple clock signals are used to convey timing information, then operational flexibility is improved, but component imperfections result in non-ideal phase offsets between clock signals
Solution Approach 1:
The patent implements a feedback mechanism where phase offsets between multiple clock signals are detected and measured, then correction signals are generated and applied back to the clock signal paths. This closed-loop feedback system continuously compensates for phase offset errors caused by component imperfections, maintaining accurate phase relationships despite manufacturing variations.
Solution Approach 2:
The patent dynamically adjusts clock signal parameters (frequency, phase, duty cycle) based on detected offset conditions. By changing these parameters in response to measured errors, the system compensates for non-ideal phase offsets and maintains accurate timing relationships across multiple clock signals.
Data Source
AI summary
Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.