Phase-Interpolated Clock Adjustment for Duty Cycle and Noise Control
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Solution Overview
Problem
Conventional duty cycle correction and frequency multiplier circuits are complex and prone to noise, necessitating a simpler and more efficient solution for adjusting clock signals.
Innovation Solution
A clock adjustment circuit and method utilizing a low-pass filter, DC control circuit, DC offset amplifier, amplifier, and integrator to filter, adjust, and generate an output clock with a controlled duty cycle, or a phase interpolator, logic circuit, and integrator to interpolate and adjust clock frequencies, thereby simplifying the process and reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional duty cycle correction circuits and frequency multipliers are used, then clock adjustment functionality is achieved, but circuit complexity increases and noise is generated
Solution Approach 1:
The patent combines the duty cycle correction function and frequency multiplication function into a single integrated circuit. The phase interpolator simultaneously performs phase adjustment and frequency multiplication, eliminating the need for separate DCC circuits and frequency multipliers. This merging reduces the total number of components, simplifies the circuit structure, and decreases noise while maintaining both functionalities.
Solution Approach 2:
The phase interpolator is designed as a multi-functional component that can perform both duty cycle correction and frequency multiplication operations. By making this single component universal, the circuit achieves multiple functions without requiring separate dedicated circuits for each function, thereby reducing overall circuit complexity and component count.
2Reliability
If conventional duty cycle correction circuits and frequency multipliers are used, then clock adjustment functionality is achieved, but noise is generated
Solution Approach 1:
By merging the DCC and frequency multiplication functions into a single phase interpolator circuit, the patent reduces the number of active components and interconnections. This consolidation minimizes the sources of electrical noise and interference that would otherwise be generated by multiple separate circuits operating in proximity, thereby reducing overall noise while maintaining functionality.
3Device complexity
If simpler circuits are used, then circuit complexity is reduced, but clock adjustment precision may deteriorate
Solution Approach 1:
The phase interpolator employs dynamic control mechanisms that allow precise adjustment of the output clock's duty cycle and frequency. The circuit uses dynamic phase adjustment techniques that maintain high precision despite the simplified structure, ensuring that duty cycle accuracy is preserved while reducing overall circuit complexity compared to conventional approaches.
Data Source
AI summary
Clock adjustment circuits and clock adjustment methods are provided. The clock adjustment circuit is configured to generate an output clock and includes a phase interpolator, a logic circuit, and an integrator. The phase interpolator is configured to generate by interpolation an intermediate clock according to a first reference clock, a second reference clock, and a control signal. The frequencies of the first reference clock, the second reference clock and the intermediate clock are substantially the same. The logic circuit is coupled to the phase interpolator and configured to generate the output clock according to the intermediate clock and one of the first reference clock and the second reference clock. The integrator is coupled to the phase interpolator and the logic circuit and configured to generate the control signal according to the output clock. The control signal varies with an average based on a duty cycle of the output clock.