Phase-Coherent Delta-Sigma Modulator for Fractional-N PLL Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing fractional-N phase-locked loops (PLLs) lose phase coherency when switching between frequencies and returning to the original frequency, due to hidden states in Delta-Sigma Modulators (DSMs) causing random phase relationships, which is critical for systems requiring multiple instances of frequency synthesizers.
Innovation Solution
A phase coherent fractional-N phase-locked loop synthesizer using a Delta-Sigma Modulator with multiple feed-forward accumulator stages, clocked by a reference clock, accumulates and multiplies sums by a fractional divide word to maintain deterministic phase relationships, controlling the divide ratio and shaping quantization noise to ensure no phase bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a Delta-Sigma Modulator is used for fractional reference frequency tuning, then the magnitude of fractional spurs near the PLL carrier is reduced, but the PLL returns to a random phase relative to the reference when tuning away and back, breaking phase coherency
Solution Approach 1:
The patent applies preliminary action by pre-clearing the hidden states of the Delta-Sigma Modulator before frequency switching operations. Specifically, the DSM is reset to a known state before tuning away from a frequency, ensuring that when returning to the original frequency, the phase relationship is deterministic rather than random. This preliminary clearing action prevents the accumulation of uncertain state information that would otherwise break phase coherency.
2Adaptability or versatility
If the PLL tunes away from one frequency to another frequency and returns to the original frequency, then frequency flexibility is achieved, but the phase relationship between the output signal and the input reference signal becomes non-deterministic
Solution Approach 1:
The patent implements feedback by monitoring the state of the Delta-Sigma Modulator and using this information to control resetting operations. The system observes when frequency switching occurs and feeds this information back to trigger appropriate reset actions, ensuring that the DSM returns to a deterministic state. This feedback mechanism maintains phase coherency while allowing frequency flexibility.
Solution Approach 2:
Before frequency switching operations, the system performs preliminary resetting of the DSM to clear hidden states. This preliminary action ensures that subsequent frequency transitions and returns maintain deterministic phase relationships, resolving the contradiction between frequency adaptability and phase reliability.
3Adaptability or versatility
If multiple instances of frequency synthesizers are used in a system, then system functionality is enhanced, but phase coherency between instances becomes critical and difficult to maintain
Solution Approach 1:
The patent applies preliminary action by resetting the Delta-Sigma Modulator to a known deterministic state before frequency switching operations. This ensures that when multiple synthesizer instances operate simultaneously or sequentially, they all start from the same phase reference point, maintaining phase coherency across instances while preserving enhanced system functionality.
Data Source
AI summary
A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.