Phase-Coherent Frequency Synthesis for Low-Overhead Frequency Hopping
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Solution Overview
Problem
Existing frequency synthesis techniques, such as Direct Digital Synthesizers (DDSs), Fractional-N Phase-Locked Loops (PLLs), and Delta-Sigma Modulators (DSMs), face challenges in maintaining phase coherency when switching between frequencies, often requiring computationally intensive operations that are impractical for many applications.
Innovation Solution
The implementation of an efficient phase coherent frequency synthesis technique that limits computationally expensive multiplication operations to only when frequency changes occur, using a system with a first phase accumulator for constant frequency periods and a second phase accumulator for frequency changes, along with a multiplexer to select between digital phase signals based on multiplication completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If computationally intensive multiplication is performed on each clock cycle to maintain phase coherency, then phase coherency is maintained, but computational complexity and power consumption increase significantly
Solution Approach 1:
The patent segments the frequency synthesis operation into two distinct modes: a first mode for frequency transitions that performs computationally intensive multiplication to establish phase coherency, and a second mode for steady-state operation that uses simpler addition-based phase accumulation. This segmentation allows the system to maintain phase coherency when needed while avoiding unnecessary computational overhead during stable frequency operation.
Solution Approach 2:
The system performs multiplication operations periodically only during frequency transitions rather than continuously on every clock cycle. The controller detects frequency transition events and triggers multiplication operations at these specific moments, while using simpler addition operations during the majority of time when frequency remains constant, thereby reducing overall computational complexity.
2Reliability
If computationally intensive multiplication is performed on each clock cycle to maintain phase coherency, then phase coherency is maintained, but power consumption increases
Solution Approach 1:
The patent segments the frequency synthesis operation into two distinct modes: a first mode for frequency transitions that performs computationally intensive multiplication to establish phase coherency, and a second mode for steady-state operation that uses simpler addition-based phase accumulation. This segmentation allows the system to maintain phase coherency when needed while avoiding unnecessary computational overhead during stable frequency operation.
Solution Approach 2:
The system performs multiplication operations periodically only during frequency transitions rather than continuously on every clock cycle. The controller detects frequency transition events and triggers multiplication operations at these specific moments, while using simpler addition operations during the majority of time when frequency remains constant, thereby reducing overall computational complexity.
3Device complexity
If simple addition is used for phase accumulation, then computational complexity is reduced, but phase coherency is lost during frequency switching
Solution Approach 1:
The patent implements a dynamic system that automatically adapts its computational approach based on operating conditions. The controller monitors frequency transition events and dynamically switches between two operational modes: using multiplication operations during frequency transitions to maintain phase coherency, and using addition operations during steady-state operation to reduce computational complexity. This dynamic adaptation resolves the contradiction by applying the appropriate computational method at the appropriate time.
Solution Approach 2:
The system performs multiplication operations periodically only during frequency transitions rather than continuously on every clock cycle. The controller detects frequency transition events and triggers multiplication operations at these specific moments, while using simpler addition operations during the majority of time when frequency remains constant, thereby reducing overall computational complexity.
4Reliability
If multiplication operations are performed frequently to maintain phase coherency during frequency hopping, then phase coherency is maintained, but processing speed decreases
Solution Approach 1:
The system performs multiplication operations periodically only during frequency transitions rather than continuously on every clock cycle. The controller detects frequency transition events and triggers multiplication operations at these specific moments, while using simpler addition operations during the majority of time when frequency remains constant, thereby reducing overall computational complexity.
Solution Approach 2:
The patent implements a dynamic system that automatically adapts its computational approach based on operating conditions. The controller monitors frequency transition events and dynamically switches between two operational modes: using multiplication operations during frequency transitions to maintain phase coherency, and using addition operations during steady-state operation to reduce computational complexity. This dynamic adaptation resolves the contradiction by applying the appropriate computational method at the appropriate time.
Data Source
AI summary
Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.