Phase-Coherent Frequency Synthesis With Event-Triggered Multiplication
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Solution Overview
Problem
Existing frequency synthesis techniques, such as Direct Digital Synthesizers (DDSs), Fractional-N Phase-Locked Loops (PLLs), and Delta-Sigma Modulators (DSMs), face challenges in maintaining phase coherency when switching between frequencies, often requiring computationally intensive operations that are impractical for many applications.
Innovation Solution
The implementation of an efficient phase coherent frequency synthesis technique that limits computationally expensive multiplication operations to only when frequency changes occur, using a system with a first phase accumulator for constant frequency periods and a second phase accumulator for frequency changes, along with a multiplexer to select between digital phase signals based on multiplication completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If computationally intensive multiplication is performed on each clock cycle to maintain phase coherency, then phase coherency is maintained, but computational overhead and power consumption increase
Solution Approach 1:
The patent implements periodic action by performing computationally intensive multiplication operations only at specific intervals (when frequency changes occur) rather than continuously on every clock cycle. The system uses a frequency change detector to trigger multiplication events, and the results are stored in buffers for use during constant frequency periods, thereby reducing computational overhead while maintaining phase coherency.
Solution Approach 2:
The patent applies preliminary action by pre-calculating phase values using multiplication operations before frequency changes occur and storing them in buffers. This allows the system to have phase coherent values ready in advance, eliminating the need for continuous multiplication during operation and reducing real-time computational requirements.
2Reliability
If computationally intensive multiplication is performed on each clock cycle to maintain phase coherency, then phase coherency is maintained, but device complexity increases
Solution Approach 1:
The system reduces device complexity by implementing periodic action - multiplication operations are performed only periodically when frequency changes are detected, rather than continuously. This is achieved through a frequency change detector that triggers multiplication events, with results buffered for later use, thereby simplifying the computational architecture.
Solution Approach 2:
The patent applies segmentation by dividing the frequency synthesis operation into distinct segments: constant frequency periods where buffered values are used, and frequency transition periods where multiplication is performed. This segmentation allows the complex multiplication operation to be isolated to specific segments, reducing overall device complexity.
3Reliability
If continuous multiplication is performed to maintain phase coherency during frequency switching, then phase coherency is maintained, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by implementing periodic action - multiplication operations consume significant power but are performed only periodically when frequency changes occur rather than continuously. The frequency change detector triggers these high-power operations only when necessary, with results buffered for use during lower-power constant frequency periods.
Solution Approach 2:
The system applies preliminary action by pre-computing phase values before frequency changes and storing them in buffers. This allows the high-power multiplication operation to be performed in advance during low-activity periods, reducing real-time power consumption while maintaining phase coherency during frequency transitions.
Data Source
AI summary
Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.